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6ab99c7ca6
Summary: This includes a hazard recognizer implementation to replace some of the hazard handling we had during frame index elimination. Reviewers: arsenm Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18602 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268143 91177308-0d34-0410-b5e6-96231b3b80d8
24 lines
1.1 KiB
LLVM
24 lines
1.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
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declare double @llvm.AMDGPU.rsq.clamped.f64(double) nounwind readnone
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; FUNC-LABEL: {{^}}rsq_clamped_f64:
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; SI: v_rsq_clamp_f64_e32
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; VI-DAG: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}]
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; TODO: this constant should be folded:
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; VI-DAG: s_mov_b32 s[[ALLBITS:[0-9+]]], -1
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; VI-DAG: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff
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; VI-DAG: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff
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; VI-DAG: s_mov_b32 s[[LOW1:[0-9+]]], s[[ALLBITS]]
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; VI: s_mov_b32 s[[LOW2:[0-9+]]], s[[ALLBITS]]
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; VI: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]]
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; VI: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW2]]:[[HIGH2]]]
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define void @rsq_clamped_f64(double addrspace(1)* %out, double %src) nounwind {
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%rsq_clamped = call double @llvm.AMDGPU.rsq.clamped.f64(double %src) nounwind readnone
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store double %rsq_clamped, double addrspace(1)* %out, align 8
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ret void
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}
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