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b762ae1118
Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260758 91177308-0d34-0410-b5e6-96231b3b80d8
43 lines
1.2 KiB
LLVM
43 lines
1.2 KiB
LLVM
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
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;
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; This checks that predicate registers are moved to GPRs instead of spilling
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; where possible.
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; CHECK: p0 =
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; CHECK-NOT: memw(r29
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define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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entry:
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%cmp = icmp eq i32 %a, 1
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%cmp1 = icmp eq i32 %b, 2
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%or.cond = and i1 %cmp, %cmp1
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%cmp3 = icmp eq i32 %c, 3
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%or.cond30 = and i1 %or.cond, %cmp3
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%cmp5 = icmp eq i32 %d, 4
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%or.cond31 = and i1 %or.cond30, %cmp5
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%cmp7 = icmp eq i32 %e, 5
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%or.cond32 = and i1 %or.cond31, %cmp7
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%ret.0 = zext i1 %or.cond32 to i32
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%cmp8 = icmp eq i32 %a, 3
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%cmp10 = icmp eq i32 %b, 4
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%or.cond33 = and i1 %cmp8, %cmp10
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%cmp12 = icmp eq i32 %c, 5
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%or.cond34 = and i1 %or.cond33, %cmp12
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%cmp14 = icmp eq i32 %d, 6
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%or.cond35 = and i1 %or.cond34, %cmp14
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%cmp16 = icmp eq i32 %e, 7
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%or.cond36 = and i1 %or.cond35, %cmp16
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%ret.1 = select i1 %or.cond36, i32 2, i32 %ret.0
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%cmp21 = icmp eq i32 %b, 8
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%or.cond37 = and i1 %cmp, %cmp21
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%cmp23 = icmp eq i32 %c, 2
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%or.cond38 = and i1 %or.cond37, %cmp23
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%cmp25 = icmp eq i32 %d, 1
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%or.cond39 = and i1 %or.cond38, %cmp25
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%cmp27 = icmp eq i32 %e, 3
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%or.cond40 = and i1 %or.cond39, %cmp27
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%ret.2 = select i1 %or.cond40, i32 3, i32 %ret.1
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ret i32 %ret.2
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}
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