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llvm/test/CodeGen/Hexagon
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Krzysztof Parzyszek af47668fd9 [Hexagon] Do not insert non-phis before phis in bit simplification 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257606 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-13 15:48:18 +00:00
..
intrinsics
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vect
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
absaddr-store.ll
[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission.
2015-11-09 04:07:48 +00:00
absimm.ll
[Hexagon] Fixing store instructions and reenabling a few more tests.
2015-11-10 00:22:00 +00:00
adde.ll
[Hexagon] Preprocess mapped instructions before lowering to MC
2015-12-15 17:05:45 +00:00
addh-sext-trunc.ll
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addh-shifted.ll
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addh.ll
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addrmode-indoff.ll
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alu64.ll
[Hexagon] Preprocess mapped instructions before lowering to MC
2015-12-15 17:05:45 +00:00
always-ext.ll
[Hexagon] Fixing load instruction parsing and reenabling tests.
2015-11-10 00:02:27 +00:00
args.ll
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ashift-left-right.ll
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Atomics.ll
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barrier-flag.ll
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base-offset-addr.ll
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base-offset-post.ll
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bit-eval.ll
[Hexagon] Preprocess mapped instructions before lowering to MC
2015-12-15 17:05:45 +00:00
bit-loop.ll
[Hexagon] Bit-based instruction simplification
2015-10-20 22:57:13 +00:00
bit-phi.ll
[Hexagon] Do not insert non-phis before phis in bit simplification
2016-01-13 15:48:18 +00:00
block-addr.ll
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BranchPredict.ll
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brev_ld.ll
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brev_st.ll
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bugAsmHWloop.ll
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calling-conv-2.ll
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cext-check.ll
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cext-valid-packet1.ll
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cext-valid-packet2.ll
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cext.ll
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cexti16.ll
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cfi-late.ll
DI: Reverse direction of subprogram -> function edge.
2015-11-05 22:03:56 +00:00
checktabs.ll
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circ_ld.ll
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circ_ldd_bug.ll
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circ_ldw.ll
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circ_st.ll
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clr_set_toggle.ll
[Hexagon] Bit-based instruction simplification
2015-10-20 22:57:13 +00:00
cmp_pred2.ll
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cmp_pred_reg.ll
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cmp_pred.ll
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cmp-extend.ll
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cmp-promote.ll
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cmp-to-genreg.ll
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cmp-to-predreg.ll
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cmp.ll
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cmpb_pred.ll
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cmpb-eq.ll
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combine_ir.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
combine.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
common-gep-basic.ll
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common-gep-icm.ll
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compound.ll
[Hexagon] Fixing compound register printing and reenabling more tests.
2015-11-10 00:51:56 +00:00
convertdptoint.ll
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convertdptoll.ll
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convertsptoint.ll
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convertsptoll.ll
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ctlz-cttz-ctpop.ll
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ctor.ll
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dadd.ll
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dmul.ll
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double.ll
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doubleconvert-ieee-rnd-near.ll
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dsub.ll
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dualstore.ll
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duplex.ll
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early-if-conversion-bug1.ll
[Hexagon] Add an early if-conversion pass
2015-10-06 15:49:14 +00:00
early-if-phi-i1.ll
[Hexagon] Add an early if-conversion pass
2015-10-06 15:49:14 +00:00
early-if-spare.ll
[Hexagon] Add an early if-conversion pass
2015-10-06 15:49:14 +00:00
early-if.ll
[Hexagon] Add an early if-conversion pass
2015-10-06 15:49:14 +00:00
eh_return.ll
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expand-condsets-basic.ll
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expand-condsets-rm-segment.ll
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expand-condsets-undef.ll
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extload-combine.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
extract-basic.ll
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fadd.ll
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fcmp.ll
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float.ll
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floatconvert-ieee-rnd-near.ll
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fmul.ll
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frame.ll
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fsub.ll
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fusedandshift.ll
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gp-plus-offset-load.ll
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gp-plus-offset-store.ll
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gp-rel.ll
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hwloop1.ll
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hwloop2.ll
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hwloop3.ll
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hwloop4.ll
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hwloop5.ll
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hwloop-cleanup.ll
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hwloop-const.ll
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hwloop-crit-edge.ll
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hwloop-dbg.ll
DI: Reverse direction of subprogram -> function edge.
2015-11-05 22:03:56 +00:00
hwloop-le.ll
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hwloop-loop1.ll
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hwloop-lt1.ll
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hwloop-lt.ll
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hwloop-missed.ll
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hwloop-ne.ll
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hwloop-ph-deadcode.ll
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hwloop-pos-ivbump1.ll
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hwloop-preheader.ll
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hwloop-range.ll
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hwloop-recursion.ll
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hwloop-wrap2.ll
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hwloop-wrap.ll
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i1_VarArg.ll
Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
2015-11-25 20:30:59 +00:00
i8_VarArg.ll
Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
2015-11-25 20:30:59 +00:00
i16_VarArg.ll
Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
2015-11-25 20:30:59 +00:00
idxload-with-zero-offset.ll
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ifcvt-edge-weight.ll
Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces.
2015-12-01 05:29:22 +00:00
indirect-br.ll
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insert-basic.ll
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lit.local.cfg
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loadi1-G0.ll
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loadi1-v4-G0.ll
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loadi1-v4.ll
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loadi1.ll
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macint.ll
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maxd.ll
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maxh.ll
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maxud.ll
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maxuw.ll
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maxw.ll
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mem-fi-add.ll
Revert "Change memcpy/memset/memmove to have dest and source alignments."
2015-11-19 05:56:52 +00:00
memcpy-likely-aligned.ll
[Hexagon] Make memcpy lowering thread-safe
2015-12-16 17:29:37 +00:00
memops1.ll
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memops2.ll
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memops3.ll
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memops.ll
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mind.ll
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minu-zext-8.ll
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minu-zext-16.ll
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minud.ll
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minuw.ll
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minw.ll
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misaligned-access.ll
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mpy.ll
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mux-basic.ll
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newvaluejump2.ll
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newvaluejump.ll
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newvaluestore.ll
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NVJumpCmp.ll
[Hexagon] Add NewValueJump support for C4_cmpneq, C4_cmplte, C4_cmplteu
2015-12-08 16:28:32 +00:00
opt-fabs.ll
[Hexagon] Bit-based instruction simplification
2015-10-20 22:57:13 +00:00
opt-fneg.ll
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packetize_cond_inst.ll
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pic-jumptables.ll
[Hexagon] Add PIC support
2015-12-18 20:19:30 +00:00
pic-simple.ll
[Hexagon] Add PIC support
2015-12-18 20:19:30 +00:00
pic-static.ll
[Hexagon] Add PIC support
2015-12-18 20:19:30 +00:00
postinc-load.ll
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postinc-offset.ll
[Hexagon] Implement RDF-based post-RA optimizations
2016-01-12 19:09:01 +00:00
postinc-store.ll
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pred-absolute-store.ll
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pred-gp.ll
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pred-instrs.ll
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predicate-copy.ll
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predicate-logical.ll
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predicate-rcmp.ll
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rdf-copy.ll
[Hexagon] Implement RDF-based post-RA optimizations
2016-01-12 19:09:01 +00:00
rdf-dead-loop.ll
[Hexagon] Implement RDF-based post-RA optimizations
2016-01-12 19:09:01 +00:00
relax.ll
[Hexagon] Delay emission of CFI instructions
2015-10-19 17:46:01 +00:00
remove_lsr.ll
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remove-endloop.ll
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sdr-basic.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
sdr-shr32.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
shrink-frame-basic.ll
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signed_immediates.ll
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simple_addend.ll
[Hexagon] Delay emission of CFI instructions
2015-10-19 17:46:01 +00:00
simpletailcall.ll
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split-const32-const64.ll
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stack-align1.ll
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stack-align2.ll
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stack-alloca1.ll
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stack-alloca2.ll
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static.ll
[Hexagon] Fixing load instruction parsing and reenabling tests.
2015-11-10 00:02:27 +00:00
store-widen-aliased-load.ll
[Hexagon] Merge adjacent stores
2015-10-16 19:43:56 +00:00
store-widen-negv2.ll
[Hexagon] Merge adjacent stores
2015-10-16 19:43:56 +00:00
store-widen-negv.ll
[Hexagon] Merge adjacent stores
2015-10-16 19:43:56 +00:00
store-widen.ll
[Hexagon] Merge adjacent stores
2015-10-16 19:43:56 +00:00
struct_args_large.ll
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struct_args.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
sube.ll
[Hexagon] Preprocess mapped instructions before lowering to MC
2015-12-15 17:05:45 +00:00
tail-call-mem-intrinsics.ll
Revert "Change memcpy/memset/memmove to have dest and source alignments."
2015-11-19 05:56:52 +00:00
tail-call-trunc.ll
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tail-dup-subreg-abort.ll
Tail duplication can mix incompatible registers in phi nodes
2015-10-21 02:40:06 +00:00
tfr-to-combine.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
union-1.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
usr-ovf-dep.ll
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v60Intrins.ll
[Hexagon] Hexagon V60 HVX intrinsic defintions
2015-11-26 16:54:33 +00:00
v60small.ll
[Hexagon] Hexagon V60 HVX intrinsic defintions
2015-11-26 16:54:33 +00:00
v60Vasr.ll
[Hexagon] Adding v60 test, vasr in particular.
2015-12-07 18:52:39 +00:00
vaddh.ll
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validate-offset.ll
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zextloadi1.ll
[Hexagon] Fixing store instructions and reenabling a few more tests.
2015-11-10 00:22:00 +00:00