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https://github.com/RPCSX/llvm.git
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9209299b97
Summary: Replace a LEA instruction of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx' MOV is preferable over LEA because usually there are more issue-slots available to execute MOVs than LEAs. Latest processors also support zero-latency MOVs. Fixes pr29022. Reviewers: hfinkel, delena, igorb, myatsina, mkuper Differential Revision: https://reviews.llvm.org/D24705 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282385 91177308-0d34-0410-b5e6-96231b3b80d8
84 lines
2.9 KiB
LLVM
84 lines
2.9 KiB
LLVM
; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
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; RUN: llc < %s -march=x86 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-32
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; RUN: llc < %s -mtriple=x86_64-pc-win32 -fast-isel | FileCheck %s --check-prefix=CHECK-W64
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=CHECK-64
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; RUN: llc < %s -mtriple=x86_64-unknown -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-64
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; RUN: llc < %s -mtriple=x86_64-gnux32 | FileCheck %s --check-prefix=CHECK-X32ABI
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; RUN: llc < %s -mtriple=x86_64-gnux32 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-X32ABI
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; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefix=CHECK-NACL64
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; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-NACL64
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define i8* @test1() nounwind {
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entry:
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; CHECK-32-LABEL: test1
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; CHECK-32: push
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; CHECK-32-NEXT: movl %esp, %ebp
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; CHECK-32-NEXT: movl %ebp, %eax
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; CHECK-32-NEXT: pop
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; CHECK-32-NEXT: ret
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; CHECK-W64-LABEL: test1
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; CHECK-W64: push
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; CHECK-W64-NEXT: movq %rsp, %rbp
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; CHECK-W64-NEXT: movq %rbp, %rax
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; CHECK-W64-NEXT: pop
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; CHECK-W64-NEXT: ret
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; CHECK-64-LABEL: test1
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; CHECK-64: push
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; CHECK-64-NEXT: movq %rsp, %rbp
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; CHECK-64-NEXT: movq %rbp, %rax
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; CHECK-64-NEXT: pop
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; CHECK-64-NEXT: ret
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; CHECK-X32ABI-LABEL: test1
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; CHECK-X32ABI: pushq %rbp
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; CHECK-X32ABI-NEXT: movl %esp, %ebp
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; CHECK-X32ABI-NEXT: movl %ebp, %eax
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; CHECK-X32ABI-NEXT: popq %rbp
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; CHECK-X32ABI-NEXT: ret
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; CHECK-NACL64-LABEL: test1
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; CHECK-NACL64: pushq %rbp
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; CHECK-NACL64-NEXT: movq %rsp, %rbp
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; CHECK-NACL64-NEXT: movl %ebp, %eax
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%0 = tail call i8* @llvm.frameaddress(i32 0)
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ret i8* %0
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}
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define i8* @test2() nounwind {
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entry:
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; CHECK-32-LABEL: test2
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; CHECK-32: push
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; CHECK-32-NEXT: movl %esp, %ebp
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; CHECK-32-NEXT: movl (%ebp), %eax
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; CHECK-32-NEXT: movl (%eax), %eax
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; CHECK-32-NEXT: pop
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; CHECK-32-NEXT: ret
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; CHECK-W64-LABEL: test2
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; CHECK-W64: push
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; CHECK-W64-NEXT: movq %rsp, %rbp
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; CHECK-W64-NEXT: movq %rbp, %rax
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; CHECK-W64-NEXT: pop
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; CHECK-W64-NEXT: ret
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; CHECK-64-LABEL: test2
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; CHECK-64: push
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; CHECK-64-NEXT: movq %rsp, %rbp
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; CHECK-64-NEXT: movq (%rbp), %rax
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; CHECK-64-NEXT: movq (%rax), %rax
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; CHECK-64-NEXT: pop
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; CHECK-64-NEXT: ret
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; CHECK-X32ABI-LABEL: test2
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; CHECK-X32ABI: pushq %rbp
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; CHECK-X32ABI-NEXT: movl %esp, %ebp
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; CHECK-X32ABI-NEXT: movl (%ebp), %eax
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; CHECK-X32ABI-NEXT: movl (%eax), %eax
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; CHECK-X32ABI-NEXT: popq %rbp
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; CHECK-X32ABI-NEXT: ret
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; CHECK-NACL64-LABEL: test2
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; CHECK-NACL64: pushq %rbp
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; CHECK-NACL64-NEXT: movq %rsp, %rbp
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; CHECK-NACL64-NEXT: movl (%ebp), %eax
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; CHECK-NACL64-NEXT: movl (%eax), %eax
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%0 = tail call i8* @llvm.frameaddress(i32 2)
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ret i8* %0
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}
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declare i8* @llvm.frameaddress(i32) nounwind readnone
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