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31333a7c12
"insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278466 91177308-0d34-0410-b5e6-96231b3b80d8
161 lines
3.9 KiB
LLVM
161 lines
3.9 KiB
LLVM
; RUN: llc -mtriple=x86_64-apple-macosx < %s | FileCheck %s
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; rdar://7610418
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%ptr = type { i8* }
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%struct.s1 = type { %ptr, %ptr }
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%struct.s2 = type { i32, i8*, i8*, [256 x %struct.s1*], [8 x i32], i64, i8*, i32, i64, i64, i32, %struct.s3*, %struct.s3*, [49 x i64] }
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%struct.s3 = type { %struct.s3*, %struct.s3*, i32, i32, i32 }
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define fastcc i8* @t(i32 %base) nounwind {
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entry:
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; CHECK-LABEL: t:
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; CHECK: leaq (%rax,%rax,4)
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%0 = zext i32 %base to i64
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%1 = getelementptr inbounds %struct.s2, %struct.s2* null, i64 %0
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br i1 undef, label %bb1, label %bb2
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bb1:
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; CHECK: %bb1
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; CHECK-NOT: shlq $9
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; CHECK-NOT: leaq
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; CHECK: call
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%2 = getelementptr inbounds %struct.s2, %struct.s2* null, i64 %0, i32 0
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call void @bar(i32* %2) nounwind
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unreachable
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bb2:
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; CHECK: %bb2
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; CHECK-NOT: leaq
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; CHECK: callq
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%3 = call fastcc i8* @foo(%struct.s2* %1) nounwind
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unreachable
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bb3:
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ret i8* undef
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}
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declare void @bar(i32*)
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declare fastcc i8* @foo(%struct.s2*) nounwind
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; rdar://8773371
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declare void @printf(...) nounwind
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define void @commute(i32 %test_case, i32 %scale) nounwind ssp {
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; CHECK-LABEL: commute:
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entry:
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switch i32 %test_case, label %sw.bb307 [
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i32 1, label %sw.bb
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i32 2, label %sw.bb
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i32 3, label %sw.bb
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]
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sw.bb: ; preds = %entry, %entry, %entry
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; CHECK: %sw.bb
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; CHECK-NOT: imull
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%mul = mul nsw i32 %test_case, 3
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%mul20 = mul nsw i32 %mul, %scale
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br i1 undef, label %if.end34, label %sw.bb307
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if.end34: ; preds = %sw.bb
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; CHECK: %if.end34
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; CHECK: imull
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; CHECK: leal
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tail call void (...) @printf(i32 %test_case, i32 %mul20) nounwind
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%tmp = mul i32 %scale, %test_case
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%tmp752 = mul i32 %tmp, 3
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%tmp753 = zext i32 %tmp752 to i64
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br label %bb.nph743.us
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for.body53.us: ; preds = %bb.nph743.us, %for.body53.us
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%exitcond = icmp eq i64 undef, %tmp753
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br i1 %exitcond, label %bb.nph743.us, label %for.body53.us
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bb.nph743.us: ; preds = %for.body53.us, %if.end34
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br label %for.body53.us
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sw.bb307: ; preds = %sw.bb, %entry
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ret void
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}
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; CSE physical register defining instruction across MBB boundary.
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; rdar://10660865
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define i32 @cross_mbb_phys_cse(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: cross_mbb_phys_cse:
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; CHECK: cmpl
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; CHECK: ja
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%cmp = icmp ugt i32 %a, %b
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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; CHECK-NOT: cmpl
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; CHECK: sbbl
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%cmp1 = icmp ult i32 %a, %b
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%. = sext i1 %cmp1 to i32
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br label %return
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return: ; preds = %if.end, %entry
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%retval.0 = phi i32 [ 1, %entry ], [ %., %if.end ]
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ret i32 %retval.0
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}
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; rdar://11393714
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define i8* @bsd_memchr(i8* %s, i32 %a, i32 %c, i64 %n) nounwind ssp {
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; CHECK: %entry
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; CHECK-NOT: xorl
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; CHECK: %preheader
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; CHECK-NOT: xorl
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; CHECK: %do.body
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; CHECK-NOT: xorl
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; CHECK: %do.cond
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; CHECK: xorl
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; CHECK: %return
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entry:
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%cmp = icmp eq i64 %n, 0
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br i1 %cmp, label %return, label %preheader
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preheader:
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%conv2 = and i32 %c, 255
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br label %do.body
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do.body:
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%n.addr.0 = phi i64 [ %dec, %do.cond ], [ %n, %preheader ]
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%p.0 = phi i8* [ %incdec.ptr, %do.cond ], [ %s, %preheader ]
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%cmp3 = icmp eq i32 %a, %conv2
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br i1 %cmp3, label %return, label %do.cond
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do.cond:
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%incdec.ptr = getelementptr inbounds i8, i8* %p.0, i64 1
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%dec = add i64 %n.addr.0, -1
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%cmp6 = icmp eq i64 %dec, 0
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br i1 %cmp6, label %return, label %do.body
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return:
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%retval.0 = phi i8* [ null, %entry ], [ null, %do.cond ], [ %p.0, %do.body ]
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ret i8* %retval.0
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}
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; PR13578
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@t2_global = external global i32
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declare i1 @t2_func()
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define i32 @t2() {
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store i32 42, i32* @t2_global
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%c = call i1 @t2_func()
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br i1 %c, label %a, label %b
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a:
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%l = load i32, i32* @t2_global
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ret i32 %l
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b:
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ret i32 0
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; CHECK-LABEL: t2:
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; CHECK: t2_global@GOTPCREL(%rip)
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; CHECK-NOT: t2_global@GOTPCREL(%rip)
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}
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