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6f0d024a53
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
149 lines
5.2 KiB
TableGen
149 lines
5.2 KiB
TableGen
// This test describes how we eventually want to describe instructions in
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// the target independent code generators.
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// RUN: tblgen %s
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// Target indep stuff.
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class Instruction { // Would have other stuff eventually
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bit isTwoAddress = 0;
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string AssemblyString;
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}
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class RegisterClass;
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class RTLNode;
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def ops; // Marker for operand list.
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// Various expressions used in RTL descriptions.
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def imm8 : RTLNode;
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def imm32 : RTLNode;
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def addr : RTLNode;
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def set : RTLNode;
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def signext : RTLNode;
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def zeroext : RTLNode;
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def plus : RTLNode;
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def and : RTLNode;
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def xor : RTLNode;
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def shl : RTLNode;
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def load : RTLNode;
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def store : RTLNode;
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def unspec : RTLNode;
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// Start of X86 specific stuff.
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def R8 : RegisterClass;
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def R16 : RegisterClass;
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def R32 : RegisterClass;
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def CL; // As are currently defined
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def AL;
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def AX;
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def EDX;
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class Format<bits<5> val> {
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bits<5> Value = val;
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}
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def Pseudo : Format<0>; def RawFrm : Format<1>;
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def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
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def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
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def MRMSrcMem : Format<6>;
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def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
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def MRM6r : Format<22>; def MRM7r : Format<23>;
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def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
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def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
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def MRM6m : Format<30>; def MRM7m : Format<31>;
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class Inst<dag opnds, string asmstr, bits<8> opcode,
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Format f, list<dag> rtl> : Instruction {
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dag Operands = opnds;
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string AssemblyString = asmstr;
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bits<8> Opcode = opcode;
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Format Format = f;
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list<dag> RTL = rtl;
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}
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// Start of instruction definitions, the real point of this file.
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//
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// Note that these patterns show a couple of important things:
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// 1. The order and contents of the operands of the MachineInstr are
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// described here. Eventually we can do away with this when everything
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// is generated from the description.
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// 2. The asm string is captured here, which makes it possible to get rid of
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// a ton of hacks in the various printers and a bunch of flags.
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// 3. Target specific properties (e.g. Format) can still be captured as
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// needed.
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// 4. We capture the behavior of the instruction with a simplified RTL-like
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// expression.
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// 5. The use/def properties for each operand are automatically inferred from
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// the pattern.
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// 6. Address expressions should become first-class entities.
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// Simple copy instruction. isMoveInstr could easily be inferred from this,
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// as could TargetRegisterInfo::copyRegToReg.
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def MOV8rr : Inst<(ops R8:$dst, R8:$src),
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"mov $dst, $src", 0x88, MRMDestReg,
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[(set R8:$dst, R8:$src)]>;
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// Simple immediate initialization.
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def MOV8ri : Inst<(ops R8:$dst, imm8:$src),
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"mov $dst, $src", 0xB0, AddRegFrm,
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[(set R8:$dst, imm8:$src)]>;
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// Two address instructions are described as three-addr instructions, with
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// the special target-independent isTwoAddress flag set. The asm pattern
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// should not refer to the $src1, this would be enforced by the
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// TargetInstrInfo tablegen backend.
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let isTwoAddress = 1 in
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def AND8rr : Inst<(ops R8:$dst, R8:$src1, R8:$src2),
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"and $dst, $src2", 0x20, MRMDestReg,
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[(set R8:$dst, (and R8:$src1, R8:$src2))]>;
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// Instructions that have explicit uses/defs make them explicit in the RTL.
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// Instructions that need extra stuff emitted in the assembly can, trivially.
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let isTwoAddress = 1 in
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def SHL32rCL : Inst<(ops R32:$dst, R32:$src),
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"shl $dst, CL", 0xD2, MRM4r,
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[(set R32:$dst, (shl R32:$src, CL))]>;
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// The RTL list is a list, allowing complex instructions to be defined easily.
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// Temporary 'internal' registers can be used to break instructions appart.
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let isTwoAddress = 1 in
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def XOR32mi : Inst<(ops addr:$addr, imm32:$imm),
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"xor $dst, $src2", 0x81, MRM6m,
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[(set R32:$tmp1, (load addr:$addr)),
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(set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
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(store addr:$addr, R32:$tmp2)]>;
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// Alternatively, if each tmporary register is only used once, the instruction
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// can just be described in nested form. This would be the canonical
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// representation the target generator would convert the above into. Pick your
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// favorite indentation scheme.
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let isTwoAddress = 1 in
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def AND32mr : Inst<(ops addr:$addr, R32:$src),
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"xor $dst, $src2", 0x81, MRM6m,
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[(store addr:$addr,
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(and
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(load addr:$addr),
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R32:$src)
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)
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]>;
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// Describing complex instructions is not too hard! Note how implicit uses/defs
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// become explicit here.
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def CBW : Inst<(ops),
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"cbw", 0x98, RawFrm,
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[(set AX, (signext AL))]>;
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// Noop, does nothing.
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def NOOP : Inst<(ops), "nop", 0x90, RawFrm, []>;
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// Instructions that don't expect optimization can use unspec.
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def IN8rr : Inst<(ops), "in AL, EDX", 0xEC, RawFrm,
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[(set AL, (unspec EDX))]>;
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