Stanislav Mekhanoshin 0bf4d71d50 Correct register pressure calculation in presence of subregs ... If a subreg is used in an instruction it counts as a whole superreg for the purpose of register pressure calculation. This patch corrects improper register pressure calculation by examining operand's lane mask. Differential Revision: https://reviews.llvm.org/D29835 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296009 91177308-0d34-0410-b5e6-96231b3b80d8		2017-02-23 20:19:44 +00:00
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AArch64	[AArch64] Extend AArch64RedundantCopyElimination to do simple copy propagation.	2017-02-22 19:10:45 +00:00
AMDGPU	Correct register pressure calculation in presence of subregs	2017-02-23 20:19:44 +00:00
ARM	[ARM] GlobalISel: Lower call returns	2017-02-23 14:18:41 +00:00
AVR	[AVR] Disable integrated assembler for a few tests	2017-02-22 22:41:13 +00:00
BPF
Generic
Hexagon	[Hexagon] Avoid IMPLICIT_DEFs as new-value producers	2017-02-23 17:47:34 +00:00
Inputs
Lanai
Mips
MIR	MIRTests: Remove unnecessary 2>&1 redirection	2017-02-22 18:47:41 +00:00
MSP430
NVPTX	[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.	2017-02-21 22:56:05 +00:00
PowerPC	[DAGCombiner] revert r295336	2017-02-22 16:27:33 +00:00
SPARC
SystemZ
Thumb	[ARM] Fix constant islands pass.	2017-02-22 09:06:21 +00:00
Thumb2
WebAssembly	[WebAssembly] Configure codegen to legalize f16 values.	2017-02-22 16:28:00 +00:00
WinEH
X86	[X86][AVX] Disable VCVTSS2SD & VCVTSD2SS memory folding and fix the register class of their first input when creating node in fast-isel.	2017-02-23 13:15:44 +00:00
XCore