Matthias Braun 0dec0e1ea5 ARM: Add scheduling information for LDRLIT instructions to swift scheduling model ... These pseudo instructions are only lowered after register allocation and are therefore still present when the machine scheduler runs. Add a run: line to a testcase that uses the uncommon flags necessary to actually produce a LDRLIT instruction on swift. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242587 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-17 23:18:26 +00:00
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Analysis	[PM/AA] Disable the core unsafe aspect of GlobalsModRef in the face of	2015-07-17 06:58:24 +00:00
Assembler
Bindings	[OCaml] Do not use -warn-error in tests.	2015-07-17 17:33:23 +00:00
Bitcode
BugPoint
CodeGen	ARM: Add scheduling information for LDRLIT instructions to swift scheduling model	2015-07-17 23:18:26 +00:00
DebugInfo	Add a "debugger tuning" concept that allows us to fine-tune how we	2015-07-15 22:04:54 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation	[asan] Fix invalid debug info for promotable allocas	2015-07-17 06:29:57 +00:00
Integer
JitListener
LibDriver	Add support for producing thin archives in llvm-lib.	2015-07-17 16:01:11 +00:00
Linker
LTO
MC	[PPC] Disassemble little endian ppc instructions in the right byte order	2015-07-15 12:56:19 +00:00
Object	Trying to fix the windows bots.	2015-07-16 00:38:34 +00:00
Other
SymbolRewriter
TableGen	[TableGen] Improve decoding options for non-orthogonal instructions	2015-07-15 08:04:27 +00:00
tools
Transforms	MergeFuncs: Transfer the function parameter attributes to the call site	2015-07-17 18:59:08 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh