James Y Knight 0e13ba8208 Sparc: Prefer reg+reg address encoding when only one register used. ...

Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces.

Futhermore, reg+imm is invalid for the (not yet supported) "alternate
address space" instructions.

Differential Revision: http://reviews.llvm.org/D8753

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236107 91177308-0d34-0410-b5e6-96231b3b80d8

2015-04-29 14:54:44 +00:00

..

AArch64

[MC] Use LShr for constant evaluation of ">>" on ELF/arm64--darwin.

2015-04-28 01:37:11 +00:00

ARM

Don't constrain the section order in tests that don't depend on it.

2015-04-29 13:55:07 +00:00

AsmParser

[MC] Use LShr for constant evaluation of ">>" on ELF/arm64--darwin.

2015-04-28 01:37:11 +00:00

COFF

Add a proper fix for pr23025.

2015-04-17 11:27:13 +00:00

Disassembler

Sparc: Prefer reg+reg address encoding when only one register used.

2015-04-29 14:54:44 +00:00

ELF

Don't constrain the section order in tests that don't depend on it.

2015-04-29 13:55:07 +00:00

Hexagon

…

MachO

MC: For variable symbols, maintain MCSymbol::Section as a cache.

2015-04-03 01:46:11 +00:00

Markup

…

Mips

[mips] [IAS] Do not generate redundant ORi in createLShiftOri.

2015-04-28 14:06:35 +00:00

PowerPC

Use CIE version 1 for .eh_frame.

2015-04-27 22:04:24 +00:00

R600

R600/SI: Add missing -mcpu=SI to assembler test

2015-04-23 19:33:55 +00:00

Sparc

Sparc: Prefer reg+reg address encoding when only one register used.

2015-04-29 14:54:44 +00:00

SystemZ

[SystemZ] Support transactional execution on zEC12

2015-04-01 12:51:43 +00:00

X86

AVX-512: Added VPMOVx2M instructions for SKX,

2015-04-21 14:38:31 +00:00