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ad0f5f6b52
Change the syntax to use `%0.sub8` to denote a subregister. This seems like a more natural fit to denote subregisters; I also plan to introduce a new ":classname" syntax in upcoming patches to denote the register class of a vreg. Note that this commit disallows plain identifiers to start with a '.' character. This shouldn't affect anything as external names/IR references are all prefixed with '$'/'%', plain identifiers are only used for instruction names, register mask names and subreg indexes. Differential Revision: https://reviews.llvm.org/D22390 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276815 91177308-0d34-0410-b5e6-96231b3b80d8
13 lines
334 B
YAML
13 lines
334 B
YAML
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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# This test ensures that an error is reported for subreg index on a physreg.
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--- |
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define void @t() { ret void }
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...
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---
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name: t
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body: |
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bb.0:
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; CHECK: [[@LINE+1]]:19: subregister index expects a virtual register
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%eax.sub_8bit = COPY %bl
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...
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