llvm/interrupt-attr-64-error.ll at 0f320a4f3b6185f61d4e3d9004b41f56bb8004ce - llvm - Gitea: Git with a cup of tea

RPCSX/llvm

mirror of https://github.com/RPCSX/llvm.git synced 2024-11-30 23:20:54 +00:00

Daniel Sanders 43733c2252 [mips] Don't derive the default ABI from the CPU in the backend.

Summary:
The backend has no reason to behave like a driver and should generally do
as it's told (and error out if it can't) instead of trying to figure out
what the API user meant. The default ABI is still derived from the arch
component as a concession to backwards compatibility.

API-users that previously passed an explicit CPU and a triple that was
inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a
different ABI to what they got before. However, it's expected that there
are no such users on the basis that CodeGen has been asserting that the
triple is consistent with the selected ABI for several releases. API-users
that were consistent or passed '' or 'generic' as the CPU will see no
difference.

Reviewers: sdardis, rafael

Subscribers: rafael, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D21466


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273557 91177308-0d34-0410-b5e6-96231b3b80d8

2016-06-23 12:42:53 +00:00

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 ; RUN: not llc -mcpu=mips64r6 -march=mipsel -target-abi n64 -relocation-model=static < %s 2>%t
 ; RUN: FileCheck %s < %t
 ; CHECK: LLVM ERROR: "interrupt" attribute is only supported for the O32 ABI on MIPS32R2+ at the present time.
 define i32 @isr_sw0() #0 {
   ret i32 0
 }
 attributes #0 = { "interrupt"="sw0" }