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Alex Lorenz 034945e8fe MIR Serialization: Create dummy functions when the MIR file doesn't have LLVM IR. 
This commit creates a dummy LLVM IR function with one basic block and an unreachable
instruction for each parsed machine function when the MIR file doesn't have LLVM IR.
This change is required as the machine function analysis pass creates machine
functions only for the functions that are defined in the current LLVM module.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10135


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239778 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 23:07:38 +00:00
..
AArch64 On behalf of Alexandros Lamprineas: 2015-06-15 15:48:44 +00:00
AMDGPU R600 -> AMDGPU rename 2015-06-13 03:28:10 +00:00
ARM [ARM] Disabling vfp4 should disable fp16 2015-06-12 09:38:51 +00:00
BPF [bpf] rename triple names bpf_be -> bpfeb 2015-06-05 16:11:14 +00:00
CPP [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
Generic Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format). 2015-05-27 18:02:19 +00:00
Hexagon [Hexagon] Using readobj rather than objdump. 2015-06-15 21:57:41 +00:00
Inputs IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Mips [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only. 2015-06-02 20:32:50 +00:00
MIR MIR Serialization: Create dummy functions when the MIR file doesn't have LLVM IR. 2015-06-15 23:07:38 +00:00
MSP430 [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
NVPTX [NVPTX] fix a crash bug in NVPTXFavorNonGenericAddrSpaces 2015-06-09 21:50:32 +00:00
PowerPC LLVM support for vector quad bit permute and gather instructions through builtins 2015-06-11 06:21:25 +00:00
SPARC Add support for the Sparc implementation-defined "ASR" registers. 2015-05-18 16:29:48 +00:00
SystemZ [DAGCombiner] Account for getVectorIdxTy() when narrowing vector load 2015-05-05 19:34:10 +00:00
Thumb Revert r238473, "Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM." 2015-06-05 18:01:28 +00:00
Thumb2 ARM: Thumb2 LDRD/STRD supports independent input/output regs 2015-06-03 16:30:24 +00:00
WinEH [WinEH] C++ EH state numbering fixes 2015-05-20 23:22:24 +00:00
X86 [X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions 2015-06-15 21:49:31 +00:00
XCore IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00