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95bb5cd8a2
This patch defines the i1 type as illegal in the X86 backend for AVX512. For DAG operations on <N x i1> types (build vector, extract vector element, ...) i8 is used, and should be truncated/extended. This should produce better scalar code for i1 types since GPRs will be used instead of mask registers. Differential Revision: https://reviews.llvm.org/D32273 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303421 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
3.3 KiB
LLVM
69 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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define i8 @test_int_x86_avx512_mask_cmp_ss(<4 x float> %a, float* %b, i8 %mask) {
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; CHECK-LABEL: test_int_x86_avx512_mask_cmp_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vcmpunordss (%rdi), %xmm0, %k0 {%k1}
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; CHECK-NEXT: kmovw %k0, %eax
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; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
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; CHECK-NEXT: retq
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%b.val = load float, float* %b
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%bv0 = insertelement <4 x float> undef, float %b.val, i32 0
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%bv1 = insertelement <4 x float> %bv0, float 0.000000e+00, i32 1
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%bv2 = insertelement <4 x float> %bv1, float 0.000000e+00, i32 2
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%bv = insertelement <4 x float> %bv2, float 0.000000e+00, i32 3
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%res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %a, <4 x float> %bv, i32 3, i8 %mask, i32 4)
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ret i8 %res2
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}
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declare i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float>, <4 x float>, i32, i8, i32)
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define <4 x float> @test_mask_max_ss(<4 x float> %a, float* %b, i8 %mask) {
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; CHECK-LABEL: test_mask_max_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vmaxss (%rdi), %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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%b.val = load float, float* %b
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%bv0 = insertelement <4 x float> undef, float %b.val, i32 0
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%bv1 = insertelement <4 x float> %bv0, float 0.000000e+00, i32 1
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%bv2 = insertelement <4 x float> %bv1, float 0.000000e+00, i32 2
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%bv = insertelement <4 x float> %bv2, float 0.000000e+00, i32 3
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%res = call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>%a, <4 x float> %bv, <4 x float> zeroinitializer, i8 %mask, i32 4)
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
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define <4 x float> @test_maskz_add_ss(<4 x float> %a, float* %b, i8 %mask) {
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; CHECK-LABEL: test_maskz_add_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vaddss (%rdi), %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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%b.val = load float, float* %b
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%bv0 = insertelement <4 x float> undef, float %b.val, i32 0
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%bv1 = insertelement <4 x float> %bv0, float 0.000000e+00, i32 1
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%bv2 = insertelement <4 x float> %bv1, float 0.000000e+00, i32 2
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%bv = insertelement <4 x float> %bv2, float 0.000000e+00, i32 3
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%res = call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>%a, <4 x float> %bv, <4 x float> zeroinitializer, i8 %mask, i32 4)
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
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declare <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32)
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define <2 x double> @test_int_x86_avx512_mask_vfmadd_sd(<2 x double> %a, <2 x double> %b, double* %c, i8 %mask){
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; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_sd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vfmadd213sd (%rdi), %xmm1, %xmm0 {%k1}
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; CHECK-NEXT: retq
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%c.val = load double, double* %c
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%cv0 = insertelement <2 x double> undef, double %c.val, i32 0
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%cv = insertelement <2 x double> %cv0, double 0.000000e+00, i32 1
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%res = call <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %a, <2 x double> %b, <2 x double> %cv, i8 %mask, i32 4)
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ret <2 x double> %res
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}
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