Jonas Paulsson c33bdfa7b1 [SystemZ] TargetTransformInfo cost functions implemented. ...

getArithmeticInstrCost(), getShuffleCost(), getCastInstrCost(),
getCmpSelInstrCost(), getVectorInstrCost(), getMemoryOpCost(),
getInterleavedMemoryOpCost() implemented.

Interleaved access vectorization enabled.

BasicTTIImpl::getCastInstrCost() improved to check for legal extending loads,
in which case the cost of the z/sext instruction becomes 0.

Review: Ulrich Weigand, Renato Golin.
https://reviews.llvm.org/D29631

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300052 91177308-0d34-0410-b5e6-96231b3b80d8

2017-04-12 11:49:08 +00:00

..

AsmParser

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Disassembler

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InstPrinter

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MCTargetDesc

Add MCContext argument to MCAsmBackend::applyFixup for error reporting

2017-04-05 10:16:14 +00:00

TargetInfo

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Utils

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AArch64.h

[globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces

2017-04-06 09:49:34 +00:00

AArch64.td

[AArch64] Crypto requires FP.

2017-04-05 10:44:38 +00:00

AArch64A53Fix835769.cpp

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AArch64A57FPLoadBalancing.cpp

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AArch64AddressTypePromotion.cpp

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AArch64AdvSIMDScalarPass.cpp

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AArch64AsmPrinter.cpp

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AArch64CallingConvention.h

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AArch64CallingConvention.td

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AArch64CallLowering.cpp

Rename AttributeSet to AttributeList

2017-03-21 16:57:19 +00:00

AArch64CallLowering.h

[GlobalISel] Use the correct calling conv for calls

2017-03-20 14:40:18 +00:00

AArch64CleanupLocalDynamicTLSPass.cpp

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AArch64CollectLOH.cpp

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AArch64ConditionalCompares.cpp

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AArch64ConditionOptimizer.cpp

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AArch64DeadRegisterDefinitionsPass.cpp

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AArch64ExpandPseudoInsts.cpp

[AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsia

2017-04-04 19:51:53 +00:00

AArch64FastISel.cpp

[AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsia

2017-04-04 19:51:53 +00:00

AArch64FrameLowering.cpp

Reduce the number of times we query the subtarget for the same information.

2017-03-31 23:12:27 +00:00

AArch64FrameLowering.h

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AArch64GenRegisterBankInfo.def

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AArch64InstrAtomics.td

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AArch64InstrFormats.td

[AArch64] [Assembler] option to disable negative immediate conversions

2017-03-28 10:02:56 +00:00

AArch64InstrInfo.cpp

[AArch64] Refine Falkor Machine Model - Part 3

2017-04-08 03:30:15 +00:00

AArch64InstrInfo.h

[AArch64] Refine Falkor Machine Model - Part 3

2017-04-08 03:30:15 +00:00

AArch64InstrInfo.td

[AArch64] [Assembler] option to disable negative immediate conversions

2017-03-28 10:02:56 +00:00

AArch64InstructionSelector.cpp

[globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces

2017-04-06 09:49:34 +00:00

AArch64ISelDAGToDAG.cpp

Revert "Instrument SDISel C++ patterns"

2017-04-01 01:26:17 +00:00

AArch64ISelLowering.cpp

[ARM/AArch64] Ensure valid vector element types for interleaved accesses

2017-04-10 18:34:37 +00:00

AArch64ISelLowering.h

[ARM/AArch64] Ensure valid vector element types for interleaved accesses

2017-04-10 18:34:37 +00:00

AArch64LegalizerInfo.cpp

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AArch64LegalizerInfo.h

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AArch64LoadStoreOptimizer.cpp

[AArch64] Use alias analysis in the load/store optimization pass.

2017-03-17 14:19:55 +00:00

AArch64MachineFunctionInfo.h

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AArch64MacroFusion.cpp

[AArch64] Simplify MacroFusion

2017-04-11 19:13:11 +00:00

AArch64MacroFusion.h

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AArch64MCInstLower.cpp

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AArch64MCInstLower.h

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AArch64PBQPRegAlloc.cpp

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AArch64PBQPRegAlloc.h

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AArch64PerfectShuffle.h

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AArch64PromoteConstant.cpp

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AArch64RedundantCopyElimination.cpp

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AArch64RegisterBankInfo.cpp

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AArch64RegisterBankInfo.h

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AArch64RegisterBanks.td

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AArch64RegisterInfo.cpp

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AArch64RegisterInfo.h

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AArch64RegisterInfo.td

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AArch64SchedA53.td

[MachineScheduler] Reference the correct header.

2017-03-26 21:27:21 +00:00

AArch64SchedA57.td

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AArch64SchedA57WriteRes.td

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AArch64SchedCyclone.td

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AArch64SchedFalkor.td

[AArch64] Refine Falkor Machine Model - Part 3

2017-04-08 03:30:15 +00:00

AArch64SchedFalkorDetails.td

[AArch64] Fix scheduling info for INS(vector, general) instruction.

2017-04-11 22:14:10 +00:00

AArch64SchedFalkorWriteRes.td

[AArch64] Fix scheduling info for INS(vector, general) instruction.

2017-04-11 22:14:10 +00:00

AArch64SchedKryo.td

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AArch64SchedKryoDetails.td

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AArch64SchedM1.td

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AArch64SchedThunderX2T99.td

[AArch64] Vulcan is now ThunderXT99

2017-03-07 19:42:40 +00:00

AArch64SchedThunderX.td

[AArch64] Vulcan is now ThunderXT99

2017-03-07 19:42:40 +00:00

AArch64Schedule.td

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AArch64SelectionDAGInfo.cpp

[AArch64] Drive-by cleanup, make this code shorter. NFCI.

2017-03-22 23:37:58 +00:00

AArch64SelectionDAGInfo.h

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AArch64StorePairSuppress.cpp

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AArch64Subtarget.cpp

[AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsia

2017-04-04 19:51:53 +00:00

AArch64Subtarget.h

[AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsia

2017-04-04 19:51:53 +00:00

AArch64SystemOperands.td

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AArch64TargetMachine.cpp

[globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces

2017-04-06 09:49:34 +00:00

AArch64TargetMachine.h

[globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces

2017-04-06 09:49:34 +00:00

AArch64TargetObjectFile.cpp

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AArch64TargetObjectFile.h

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AArch64TargetTransformInfo.cpp

[SystemZ] TargetTransformInfo cost functions implemented.

2017-04-12 11:49:08 +00:00

AArch64TargetTransformInfo.h

[SystemZ] TargetTransformInfo cost functions implemented.

2017-04-12 11:49:08 +00:00

AArch64VectorByElementOpt.cpp

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CMakeLists.txt

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LLVMBuild.txt

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