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3c55c54a87
- Added a new format for instructions where the source register is implied and it is same as the destination register. Used for pseudo instructions that clear the destination register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25872 91177308-0d34-0410-b5e6-96231b3b80d8
144 lines
6.1 KiB
C++
144 lines
6.1 KiB
C++
//===- X86.td - Target definition file for the Intel X86 arch ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a target description file for the Intel i386 architecture, refered to
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// here as the "X86" architecture.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// X86 Subtarget features.
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//
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def Feature64Bit : SubtargetFeature<"64bit", "Is64Bit", "true",
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"Enable 64-bit instructions">;
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def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
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"Enable MMX instructions">;
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def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
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"Enable SSE instructions">;
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def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
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"Enable SSE2 instructions">;
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def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
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"Enable SSE3 instructions">;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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"Enable 3DNow! instructions">;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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"Enable 3DNow! Athlon instructions">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def : Proc<"i386", []>;
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def : Proc<"i486", []>;
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def : Proc<"pentium", []>;
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def : Proc<"pentium-mmx", [FeatureMMX]>;
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def : Proc<"i686", []>;
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def : Proc<"pentiumpro", []>;
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def : Proc<"pentium2", [FeatureMMX]>;
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def : Proc<"pentium3", [FeatureMMX, FeatureSSE1]>;
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def : Proc<"pentium-m", [FeatureMMX, FeatureSSE1, FeatureSSE2]>;
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def : Proc<"pentium4", [FeatureMMX, FeatureSSE1, FeatureSSE2]>;
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def : Proc<"x86-64", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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Feature64Bit]>;
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def : Proc<"yonah", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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FeatureSSE3]>;
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def : Proc<"prescott", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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FeatureSSE3]>;
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def : Proc<"nocona", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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FeatureSSE3, Feature64Bit]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
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def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
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def : Proc<"athlon", [FeatureMMX, Feature3DNow, Feature3DNowA]>;
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def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNow, Feature3DNowA]>;
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def : Proc<"athlon-4", [FeatureMMX, FeatureSSE1, Feature3DNow,
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Feature3DNowA]>;
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def : Proc<"athlon-xp", [FeatureMMX, FeatureSSE1, Feature3DNow,
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Feature3DNowA]>;
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def : Proc<"athlon-mp", [FeatureMMX, FeatureSSE1, Feature3DNow,
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Feature3DNowA]>;
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def : Proc<"k8", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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Feature3DNow, Feature3DNowA, Feature64Bit]>;
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def : Proc<"opteron", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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Feature3DNow, Feature3DNowA, Feature64Bit]>;
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def : Proc<"athlon64", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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Feature3DNow, Feature3DNowA, Feature64Bit]>;
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def : Proc<"athlon-fx", [FeatureMMX, FeatureSSE1, FeatureSSE2,
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Feature3DNow, Feature3DNowA, Feature64Bit]>;
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def : Proc<"winchip-c6", [FeatureMMX]>;
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def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
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def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
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def : Proc<"c3-2", [FeatureMMX, FeatureSSE1]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "X86RegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "X86InstrInfo.td"
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def X86InstrInfo : InstrInfo {
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// Define how we want to layout our TargetSpecific information field... This
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// should be kept up-to-date with the fields in the X86InstrInfo.h file.
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let TSFlagsFields = ["FormBits",
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"hasOpSizePrefix",
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"Prefix",
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"ImmTypeBits",
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"FPFormBits",
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"Opcode"];
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let TSFlagsShifts = [0,
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6,
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7,
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11,
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13,
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17];
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}
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// The X86 target supports two different syntaxes for emitting machine code.
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// This is controlled by the -x86-asm-syntax={att|intel}
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def ATTAsmWriter : AsmWriter {
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string AsmWriterClassName = "ATTAsmPrinter";
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int Variant = 0;
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}
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def IntelAsmWriter : AsmWriter {
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string AsmWriterClassName = "IntelAsmPrinter";
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int Variant = 1;
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}
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def X86 : Target {
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// Specify the callee saved registers.
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let CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
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// Yes, pointers are 32-bits in size.
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let PointerType = i32;
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// Information about the instructions...
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let InstructionSet = X86InstrInfo;
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let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
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}
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