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4dd33e6269
This shares detection logic with ARM(32), since AArch64 capable CPUs may also run in 32-bit system mode. We observe weird /proc/cpuinfo output for MSM8992 and MSM8994, where they report all CPU cores as one single model, depending on which CPU core the kernel is running on. As a workaround, we hardcode the known CPU part name for these SoCs. For big.LITTLE systems, this patch would only return the part name of the first core (usually the little core). Proper support will be added in a follow-up change. Differential Revision: D31675 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299458 91177308-0d34-0410-b5e6-96231b3b80d8
117 lines
3.6 KiB
C++
117 lines
3.6 KiB
C++
//========- unittests/Support/Host.cpp - Host.cpp tests --------------========//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/Host.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Triple.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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class HostTest : public testing::Test {
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Triple Host;
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protected:
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bool isSupportedArchAndOS() {
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// Initially this is only testing detection of the number of
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// physical cores, which is currently only supported/tested for
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// x86_64 Linux and Darwin.
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return (Host.getArch() == Triple::x86_64 &&
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(Host.isOSDarwin() || Host.getOS() == Triple::Linux));
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}
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HostTest() : Host(Triple::normalize(sys::getProcessTriple())) {}
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};
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TEST_F(HostTest, NumPhysicalCores) {
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int Num = sys::getHostNumPhysicalCores();
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if (isSupportedArchAndOS())
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ASSERT_GT(Num, 0);
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else
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ASSERT_EQ(Num, -1);
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}
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TEST(getLinuxHostCPUName, ARM) {
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StringRef CortexA9ProcCpuinfo = R"(
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processor : 0
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model name : ARMv7 Processor rev 10 (v7l)
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BogoMIPS : 1393.66
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Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
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CPU implementer : 0x41
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CPU architecture: 7
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CPU variant : 0x2
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CPU part : 0xc09
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CPU revision : 10
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processor : 1
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model name : ARMv7 Processor rev 10 (v7l)
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BogoMIPS : 1393.66
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Features : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
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CPU implementer : 0x41
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CPU architecture: 7
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CPU variant : 0x2
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CPU part : 0xc09
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CPU revision : 10
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Hardware : Generic OMAP4 (Flattened Device Tree)
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Revision : 0000
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Serial : 0000000000000000
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)";
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EXPECT_EQ(sys::detail::getHostCPUNameForARM(CortexA9ProcCpuinfo),
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"cortex-a9");
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
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"CPU part : 0xc0f"),
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"cortex-a15");
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// Verify that both CPU implementer and CPU part are checked:
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x40\n"
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"CPU part : 0xc0f"),
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"generic");
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
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"CPU part : 0x06f"),
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"krait");
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}
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TEST(getLinuxHostCPUName, AArch64) {
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
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"CPU part : 0xd03"),
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"cortex-a53");
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// Verify that both CPU implementer and CPU part are checked:
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x40\n"
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"CPU part : 0xd03"),
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"generic");
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
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"CPU part : 0x201"),
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"kryo");
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// MSM8992/4 weirdness
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StringRef MSM8992ProcCpuInfo = R"(
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Processor : AArch64 Processor rev 3 (aarch64)
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processor : 0
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processor : 1
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processor : 2
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processor : 3
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processor : 4
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processor : 5
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Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
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CPU implementer : 0x41
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CPU architecture: 8
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CPU variant : 0x0
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CPU part : 0xd03
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CPU revision : 3
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Hardware : Qualcomm Technologies, Inc MSM8992
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)";
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EXPECT_EQ(sys::detail::getHostCPUNameForARM(MSM8992ProcCpuInfo),
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"cortex-a53");
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}
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