llvm/test/CodeGen/AMDGPU/trunc-vector-store-assertion-failure.ll
Tom Stellard 953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00

21 lines
565 B
LLVM

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; This tests for a bug in the SelectionDAG where custom lowered truncated
; vector stores at the end of a basic block were not being added to the
; LegalizedNodes list, which triggered an assertion failure.
; CHECK-LABEL: {{^}}test:
; CHECK: MEM_RAT_CACHELESS STORE_RAW
define void @test(<4 x i8> addrspace(1)* %out, i32 %cond, <4 x i8> %in) {
entry:
%0 = icmp eq i32 %cond, 0
br i1 %0, label %if, label %done
if:
store <4 x i8> %in, <4 x i8> addrspace(1)* %out
br label %done
done:
ret void
}