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69ada669bc
The way the named arguments for various system instructions are handled at the
moment has a few problems:
- Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
- That weird Mapping class that I have no idea what I was on when I thought
it was a good idea.
- Searches are performed linearly through the entire list.
- We print absolutely all registers in upper-case, even though some are
canonically mixed case (SPSel for example).
- The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated
to comments in our implementation, with a slightly opaque hex value
indicating the canonical encoding LLVM will use.
This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274576 91177308-0d34-0410-b5e6-96231b3b80d8
38 lines
844 B
CMake
38 lines
844 B
CMake
set(LLVM_LINK_COMPONENTS Support)
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add_tablegen(llvm-tblgen LLVM
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AsmMatcherEmitter.cpp
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AsmWriterEmitter.cpp
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AsmWriterInst.cpp
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Attributes.cpp
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CallingConvEmitter.cpp
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CodeEmitterGen.cpp
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CodeGenDAGPatterns.cpp
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CodeGenInstruction.cpp
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CodeGenMapTable.cpp
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CodeGenRegisters.cpp
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CodeGenSchedule.cpp
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CodeGenTarget.cpp
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DAGISelEmitter.cpp
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DAGISelMatcherEmitter.cpp
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DAGISelMatcherGen.cpp
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DAGISelMatcherOpt.cpp
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DAGISelMatcher.cpp
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DFAPacketizerEmitter.cpp
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DisassemblerEmitter.cpp
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FastISelEmitter.cpp
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FixedLenDecoderEmitter.cpp
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InstrInfoEmitter.cpp
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IntrinsicEmitter.cpp
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OptParserEmitter.cpp
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PseudoLoweringEmitter.cpp
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RegisterInfoEmitter.cpp
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SearchableTableEmitter.cpp
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SubtargetEmitter.cpp
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TableGen.cpp
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X86DisassemblerTables.cpp
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X86ModRMFilters.cpp
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X86RecognizableInstr.cpp
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CTagsEmitter.cpp
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)
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