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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
132 lines
3.4 KiB
LLVM
132 lines
3.4 KiB
LLVM
; RUN: opt -S -instcombine < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
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define <4 x i32> @test1(<4 x i32>* %h) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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%vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
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; CHECK-LABEL: @test1
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; CHECK: @llvm.ppc.altivec.lvx
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; CHECK: ret <4 x i32>
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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%a = add <4 x i32> %v0, %vl
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ret <4 x i32> %a
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}
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define <4 x i32> @test1a(<4 x i32>* align 16 %h) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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%vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
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; CHECK-LABEL: @test1a
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; CHECK-NOT: @llvm.ppc.altivec.lvx
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; CHECK: ret <4 x i32>
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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%a = add <4 x i32> %v0, %vl
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ret <4 x i32> %a
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}
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declare void @llvm.ppc.altivec.stvx(<4 x i32>, i8*) #0
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define <4 x i32> @test2(<4 x i32>* %h, <4 x i32> %d) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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call void @llvm.ppc.altivec.stvx(<4 x i32> %d, i8* %hv)
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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ret <4 x i32> %v0
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; CHECK-LABEL: @test2
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; CHECK: @llvm.ppc.altivec.stvx
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; CHECK: ret <4 x i32>
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}
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define <4 x i32> @test2a(<4 x i32>* align 16 %h, <4 x i32> %d) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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call void @llvm.ppc.altivec.stvx(<4 x i32> %d, i8* %hv)
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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ret <4 x i32> %v0
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; CHECK-LABEL: @test2
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; CHECK-NOT: @llvm.ppc.altivec.stvx
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; CHECK: ret <4 x i32>
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}
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declare <4 x i32> @llvm.ppc.altivec.lvxl(i8*) #1
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define <4 x i32> @test1l(<4 x i32>* %h) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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%vl = call <4 x i32> @llvm.ppc.altivec.lvxl(i8* %hv)
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; CHECK-LABEL: @test1l
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; CHECK: @llvm.ppc.altivec.lvxl
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; CHECK: ret <4 x i32>
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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%a = add <4 x i32> %v0, %vl
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ret <4 x i32> %a
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}
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define <4 x i32> @test1la(<4 x i32>* align 16 %h) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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%vl = call <4 x i32> @llvm.ppc.altivec.lvxl(i8* %hv)
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; CHECK-LABEL: @test1la
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; CHECK-NOT: @llvm.ppc.altivec.lvxl
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; CHECK: ret <4 x i32>
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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%a = add <4 x i32> %v0, %vl
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ret <4 x i32> %a
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}
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declare void @llvm.ppc.altivec.stvxl(<4 x i32>, i8*) #0
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define <4 x i32> @test2l(<4 x i32>* %h, <4 x i32> %d) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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call void @llvm.ppc.altivec.stvxl(<4 x i32> %d, i8* %hv)
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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ret <4 x i32> %v0
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; CHECK-LABEL: @test2l
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; CHECK: @llvm.ppc.altivec.stvxl
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; CHECK: ret <4 x i32>
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}
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define <4 x i32> @test2la(<4 x i32>* align 16 %h, <4 x i32> %d) #0 {
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entry:
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%h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1
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%hv = bitcast <4 x i32>* %h1 to i8*
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call void @llvm.ppc.altivec.stvxl(<4 x i32> %d, i8* %hv)
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%v0 = load <4 x i32>, <4 x i32>* %h, align 8
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ret <4 x i32> %v0
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; CHECK-LABEL: @test2l
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; CHECK-NOT: @llvm.ppc.altivec.stvxl
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; CHECK: ret <4 x i32>
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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