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1c23594d2c
This patch corresponds to review: http://reviews.llvm.org/D15286 LLVM IR frequently contains bitcast operations between floating point and integer values of the same width. Doing this through memory operations is quite expensive on PPC. This patch allows the use of direct register moves between FPRs and GPRs for lowering bitcasts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255246 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
4.3 KiB
LLVM
115 lines
4.3 KiB
LLVM
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-BE
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; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-P7
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @geti(<4 x i32> %a, i32 signext %b) {
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entry:
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%vecext = extractelement <4 x i32> %a, i32 %b
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ret i32 %vecext
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; CHECK-LABEL: @geti
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; CHECK-P7-LABEL: @geti
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; CHECK-BE-LABEL: @geti
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; CHECK-DAG: li [[TRUNCREG:[0-9]+]], 2
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; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
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; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 2
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; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
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; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]]
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; CHECK-DAG: li [[ONEREG:[0-9]+]], 1
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; CHECK-DAG: and [[ELEMSREG:[0-9]+]], [[ONEREG]], 5
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; CHECK-DAG: sldi [[SHAMREG:[0-9]+]], [[ELEMSREG]], 5
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; CHECK: mfvsrd [[TOGPR:[0-9]+]],
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; CHECK: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]]
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; CHECK: extsw 3, [[RSHREG]]
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; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 2
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; CHECK-P7-DAG: stxvw4x 34,
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; CHECK-P7: lwax 3, [[ELEMOFFREG]],
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; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 2
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; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 2
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; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
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; CHECK-BE-DAG: li [[IMMREG:[0-9]+]], 1
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; CHECK-BE-DAG: andc [[ANDCREG:[0-9]+]], [[IMMREG]], 5
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; CHECK-BE-DAG: sldi [[SHAMREG:[0-9]+]], [[ANDCREG]], 5
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; CHECK-BE: mfvsrd [[TOGPR:[0-9]+]],
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; CHECK-BE: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]]
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; CHECk-BE: extsw 3, [[RSHREG]]
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @getl(<2 x i64> %a, i32 signext %b) {
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entry:
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%vecext = extractelement <2 x i64> %a, i32 %b
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ret i64 %vecext
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; CHECK-LABEL: @getl
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; CHECK-P7-LABEL: @getl
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; CHECK-BE-LABEL: @getl
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; CHECK-DAG: li [[TRUNCREG:[0-9]+]], 1
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; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
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; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3
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; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
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; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]]
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; CHECK: mfvsrd 3,
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; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 3
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; CHECK-P7-DAG: stxvd2x 34,
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; CHECK-P7: ldx 3, [[ELEMOFFREG]],
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; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1
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; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3
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; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
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; CHECK-BE: mfvsrd 3,
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}
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; Function Attrs: norecurse nounwind readnone
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define float @getf(<4 x float> %a, i32 signext %b) {
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entry:
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%vecext = extractelement <4 x float> %a, i32 %b
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ret float %vecext
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; CHECK-LABEL: @getf
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; CHECK-P7-LABEL: @getf
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; CHECK-BE-LABEL: @getf
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; CHECK: li [[IMMREG:[0-9]+]], 3
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; CHECK: xor [[TRUNCREG:[0-9]+]], [[IMMREG]], 5
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; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[TRUNCREG]]
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; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
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; CHECK: xscvspdpn 1,
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; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 2
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; CHECK-P7-DAG: stxvw4x 34,
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; CHECK-P7: lfsx 1, [[ELEMOFFREG]],
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; CHECK-BE: sldi [[ELNOREG:[0-9]+]], 5, 2
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; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]]
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; CHECK-BE: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
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; CHECK-BE: xscvspdpn 1,
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}
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; Function Attrs: norecurse nounwind readnone
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define double @getd(<2 x double> %a, i32 signext %b) {
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entry:
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%vecext = extractelement <2 x double> %a, i32 %b
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ret double %vecext
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; CHECK-LABEL: @getd
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; CHECK-P7-LABEL: @getd
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; CHECK-BE-LABEL: @getd
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; CHECK: li [[TRUNCREG:[0-9]+]], 1
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; CHECK: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
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; CHECK: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3
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; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
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; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
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; FIXME: the instruction below is a redundant regclass copy, to be removed
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; CHECK: xxlor 1,
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; CHECK-P7-DAG: andi. [[ANDREG:[0-9]+]], 5, 1
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; CHECK-P7-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3
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; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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; CHECK-P7-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
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; FIXME: the instruction below is a redundant regclass copy, to be removed
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; CHECK-P7: xxlor 1,
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; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1
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; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3
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; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
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; FIXME: the instruction below is a redundant regclass copy, to be removed
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; CHECK-BE: xxlor 1,
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}
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