llvm/test/CodeGen/ARM/2010-12-07-PEIBug.ll
Tim Northover d4517fa24d ARM: correct Dwarf output for non-contiguous VFP saves.
When the list of VFP registers to be saved was non-contiguous (so multiple
vpush/vpop instructions were needed) these were being ordered oddly, as in:
    vpush {d8, d9}
    vpush {d11}

This led to the layout in memory being [d11, d8, d9] which is ugly and doesn't
match the CFI_INSTRUCTIONs we're generating either (so Dwarf info would be
broken).

This switches the order of vpush/vpop (in both prologue and epilogue,
obviously) so that the Dwarf locations are correct again.

rdar://problem/16264856

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203655 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 11:29:23 +00:00

17 lines
417 B
LLVM

; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a9 | FileCheck %s
; rdar://8728956
define hidden void @foo() nounwind ssp {
entry:
; CHECK-LABEL: foo:
; CHECK: mov r7, sp
; CHECK-NEXT: vpush {d10, d11}
; CHECK-NEXT: vpush {d8}
tail call void asm sideeffect "","~{d8},~{d10},~{d11}"() nounwind
; CHECK: vpop {d8}
; CHECK-NEXT: vpop {d10, d11}
ret void
}
declare hidden float @bar() nounwind readnone ssp