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1b91bcddd5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133171 91177308-0d34-0410-b5e6-96231b3b80d8
968 lines
41 KiB
TableGen
968 lines
41 KiB
TableGen
//===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the PTX instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "PTXInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Code Generation Predicates
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//===----------------------------------------------------------------------===//
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// Addressing
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def Use32BitAddresses : Predicate<"!getSubtarget().is64Bit()">;
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def Use64BitAddresses : Predicate<"getSubtarget().is64Bit()">;
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// Shader Model Support
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def SupportsSM13 : Predicate<"getSubtarget().supportsSM13()">;
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def DoesNotSupportSM13 : Predicate<"!getSubtarget().supportsSM13()">;
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def SupportsSM20 : Predicate<"getSubtarget().supportsSM20()">;
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def DoesNotSupportSM20 : Predicate<"!getSubtarget().supportsSM20()">;
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// PTX Version Support
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def SupportsPTX21 : Predicate<"getSubtarget().supportsPTX21()">;
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def DoesNotSupportPTX21 : Predicate<"!getSubtarget().supportsPTX21()">;
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def SupportsPTX22 : Predicate<"getSubtarget().supportsPTX22()">;
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def DoesNotSupportPTX22 : Predicate<"!getSubtarget().supportsPTX22()">;
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def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">;
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def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">;
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// Fused-Multiply Add
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def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">;
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def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">;
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::GLOBAL;
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return false;
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}]>;
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def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::CONSTANT;
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return false;
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}]>;
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def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::LOCAL;
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return false;
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}]>;
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def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::PARAMETER;
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return false;
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}]>;
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def load_shared : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::SHARED;
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return false;
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}]>;
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def store_global
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::GLOBAL;
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return false;
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}]>;
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def store_local
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::LOCAL;
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return false;
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}]>;
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def store_parameter
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::PARAMETER;
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return false;
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}]>;
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def store_shared
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::SHARED;
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return false;
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}]>;
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// Addressing modes.
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def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
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def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
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def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
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def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
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def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
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def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
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// Address operands
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def MEMri32 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops RegI32, i32imm);
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}
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def MEMri64 : Operand<i64> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops RegI64, i64imm);
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}
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def MEMii32 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops i32imm, i32imm);
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}
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def MEMii64 : Operand<i64> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops i64imm, i64imm);
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}
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// The operand here does not correspond to an actual address, so we
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// can use i32 in 64-bit address modes.
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def MEMpi : Operand<i32> {
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let PrintMethod = "printParamOperand";
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let MIOperandInfo = (ops i32imm);
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}
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// Branch & call targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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//===----------------------------------------------------------------------===//
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// PTX Specific Node Definitions
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//===----------------------------------------------------------------------===//
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// PTX allow generic 3-reg shifts like shl r0, r1, r2
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def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
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def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
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def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
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def PTXexit
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: SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
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def PTXret
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: SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
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def PTXcopyaddress
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: SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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//===- Floating-Point Instructions - 2 Operand Form -----------------------===//
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multiclass PTX_FLOAT_2OP<string opcstr, SDNode opnode> {
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def rr32 : InstPTX<(outs RegF32:$d),
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(ins RegF32:$a),
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!strconcat(opcstr, ".f32\t$d, $a"),
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[(set RegF32:$d, (opnode RegF32:$a))]>;
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def ri32 : InstPTX<(outs RegF32:$d),
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(ins f32imm:$a),
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!strconcat(opcstr, ".f32\t$d, $a"),
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[(set RegF32:$d, (opnode fpimm:$a))]>;
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def rr64 : InstPTX<(outs RegF64:$d),
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(ins RegF64:$a),
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!strconcat(opcstr, ".f64\t$d, $a"),
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[(set RegF64:$d, (opnode RegF64:$a))]>;
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def ri64 : InstPTX<(outs RegF64:$d),
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(ins f64imm:$a),
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!strconcat(opcstr, ".f64\t$d, $a"),
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[(set RegF64:$d, (opnode fpimm:$a))]>;
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}
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//===- Floating-Point Instructions - 3 Operand Form -----------------------===//
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multiclass PTX_FLOAT_3OP<string opcstr, SDNode opnode> {
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def rr32 : InstPTX<(outs RegF32:$d),
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(ins RegF32:$a, RegF32:$b),
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!strconcat(opcstr, ".f32\t$d, $a, $b"),
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[(set RegF32:$d, (opnode RegF32:$a, RegF32:$b))]>;
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def ri32 : InstPTX<(outs RegF32:$d),
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(ins RegF32:$a, f32imm:$b),
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!strconcat(opcstr, ".f32\t$d, $a, $b"),
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[(set RegF32:$d, (opnode RegF32:$a, fpimm:$b))]>;
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def rr64 : InstPTX<(outs RegF64:$d),
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(ins RegF64:$a, RegF64:$b),
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!strconcat(opcstr, ".f64\t$d, $a, $b"),
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[(set RegF64:$d, (opnode RegF64:$a, RegF64:$b))]>;
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def ri64 : InstPTX<(outs RegF64:$d),
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(ins RegF64:$a, f64imm:$b),
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!strconcat(opcstr, ".f64\t$d, $a, $b"),
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[(set RegF64:$d, (opnode RegF64:$a, fpimm:$b))]>;
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}
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//===- Floating-Point Instructions - 4 Operand Form -----------------------===//
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multiclass PTX_FLOAT_4OP<string opcstr, SDNode opnode1, SDNode opnode2> {
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def rrr32 : InstPTX<(outs RegF32:$d),
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(ins RegF32:$a, RegF32:$b, RegF32:$c),
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!strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
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[(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
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RegF32:$b),
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RegF32:$c))]>;
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def rri32 : InstPTX<(outs RegF32:$d),
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(ins RegF32:$a, RegF32:$b, f32imm:$c),
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!strconcat(opcstr, ".f32\t$d, $a, $b, $c"),
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[(set RegF32:$d, (opnode2 (opnode1 RegF32:$a,
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RegF32:$b),
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fpimm:$c))]>;
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def rrr64 : InstPTX<(outs RegF64:$d),
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(ins RegF64:$a, RegF64:$b, RegF64:$c),
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!strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
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[(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
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RegF64:$b),
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RegF64:$c))]>;
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def rri64 : InstPTX<(outs RegF64:$d),
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(ins RegF64:$a, RegF64:$b, f64imm:$c),
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!strconcat(opcstr, ".f64\t$d, $a, $b, $c"),
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[(set RegF64:$d, (opnode2 (opnode1 RegF64:$a,
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RegF64:$b),
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fpimm:$c))]>;
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}
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multiclass INT3<string opcstr, SDNode opnode> {
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def rr16 : InstPTX<(outs RegI16:$d),
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(ins RegI16:$a, RegI16:$b),
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!strconcat(opcstr, ".u16\t$d, $a, $b"),
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[(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
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def ri16 : InstPTX<(outs RegI16:$d),
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(ins RegI16:$a, i16imm:$b),
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!strconcat(opcstr, ".u16\t$d, $a, $b"),
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[(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
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def rr32 : InstPTX<(outs RegI32:$d),
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(ins RegI32:$a, RegI32:$b),
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!strconcat(opcstr, ".u32\t$d, $a, $b"),
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[(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
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def ri32 : InstPTX<(outs RegI32:$d),
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(ins RegI32:$a, i32imm:$b),
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!strconcat(opcstr, ".u32\t$d, $a, $b"),
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[(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
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def rr64 : InstPTX<(outs RegI64:$d),
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(ins RegI64:$a, RegI64:$b),
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!strconcat(opcstr, ".u64\t$d, $a, $b"),
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[(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
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def ri64 : InstPTX<(outs RegI64:$d),
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(ins RegI64:$a, i64imm:$b),
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!strconcat(opcstr, ".u64\t$d, $a, $b"),
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[(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
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}
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multiclass PTX_LOGIC<string opcstr, SDNode opnode> {
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def ripreds : InstPTX<(outs RegPred:$d),
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(ins RegPred:$a, i1imm:$b),
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!strconcat(opcstr, ".pred\t$d, $a, $b"),
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[(set RegPred:$d, (opnode RegPred:$a, imm:$b))]>;
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def rrpreds : InstPTX<(outs RegPred:$d),
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(ins RegPred:$a, RegPred:$b),
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!strconcat(opcstr, ".pred\t$d, $a, $b"),
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[(set RegPred:$d, (opnode RegPred:$a, RegPred:$b))]>;
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def rr16 : InstPTX<(outs RegI16:$d),
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(ins RegI16:$a, RegI16:$b),
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!strconcat(opcstr, ".b16\t$d, $a, $b"),
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[(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
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def ri16 : InstPTX<(outs RegI16:$d),
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(ins RegI16:$a, i16imm:$b),
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!strconcat(opcstr, ".b16\t$d, $a, $b"),
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[(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
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def rr32 : InstPTX<(outs RegI32:$d),
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(ins RegI32:$a, RegI32:$b),
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!strconcat(opcstr, ".b32\t$d, $a, $b"),
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[(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
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def ri32 : InstPTX<(outs RegI32:$d),
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(ins RegI32:$a, i32imm:$b),
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!strconcat(opcstr, ".b32\t$d, $a, $b"),
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[(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
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def rr64 : InstPTX<(outs RegI64:$d),
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(ins RegI64:$a, RegI64:$b),
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!strconcat(opcstr, ".b64\t$d, $a, $b"),
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[(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
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def ri64 : InstPTX<(outs RegI64:$d),
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(ins RegI64:$a, i64imm:$b),
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!strconcat(opcstr, ".b64\t$d, $a, $b"),
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[(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
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}
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multiclass INT3ntnc<string opcstr, SDNode opnode> {
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def rr16 : InstPTX<(outs RegI16:$d),
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(ins RegI16:$a, RegI16:$b),
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!strconcat(opcstr, "16\t$d, $a, $b"),
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[(set RegI16:$d, (opnode RegI16:$a, RegI16:$b))]>;
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def rr32 : InstPTX<(outs RegI32:$d),
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(ins RegI32:$a, RegI32:$b),
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!strconcat(opcstr, "32\t$d, $a, $b"),
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[(set RegI32:$d, (opnode RegI32:$a, RegI32:$b))]>;
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def rr64 : InstPTX<(outs RegI64:$d),
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(ins RegI64:$a, RegI64:$b),
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!strconcat(opcstr, "64\t$d, $a, $b"),
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[(set RegI64:$d, (opnode RegI64:$a, RegI64:$b))]>;
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def ri16 : InstPTX<(outs RegI16:$d),
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(ins RegI16:$a, i16imm:$b),
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!strconcat(opcstr, "16\t$d, $a, $b"),
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[(set RegI16:$d, (opnode RegI16:$a, imm:$b))]>;
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def ri32 : InstPTX<(outs RegI32:$d),
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(ins RegI32:$a, i32imm:$b),
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!strconcat(opcstr, "32\t$d, $a, $b"),
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[(set RegI32:$d, (opnode RegI32:$a, imm:$b))]>;
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def ri64 : InstPTX<(outs RegI64:$d),
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(ins RegI64:$a, i64imm:$b),
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!strconcat(opcstr, "64\t$d, $a, $b"),
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[(set RegI64:$d, (opnode RegI64:$a, imm:$b))]>;
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def ir16 : InstPTX<(outs RegI16:$d),
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(ins i16imm:$a, RegI16:$b),
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!strconcat(opcstr, "16\t$d, $a, $b"),
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[(set RegI16:$d, (opnode imm:$a, RegI16:$b))]>;
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def ir32 : InstPTX<(outs RegI32:$d),
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(ins i32imm:$a, RegI32:$b),
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!strconcat(opcstr, "32\t$d, $a, $b"),
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[(set RegI32:$d, (opnode imm:$a, RegI32:$b))]>;
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def ir64 : InstPTX<(outs RegI64:$d),
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(ins i64imm:$a, RegI64:$b),
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!strconcat(opcstr, "64\t$d, $a, $b"),
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[(set RegI64:$d, (opnode imm:$a, RegI64:$b))]>;
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}
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multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
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CondCode cmp, string cmpstr> {
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// TODO support 5-operand format: p|q, a, b, c
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def rr
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: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
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!strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
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[(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>;
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def ri
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: InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
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!strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
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[(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>;
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def rr_and_r
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: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
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!strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
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[(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
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def ri_and_r
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: InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
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!strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
|
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[(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
|
|
def rr_or_r
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
|
|
[(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
|
|
def ri_or_r
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
|
|
[(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
|
|
def rr_xor_r
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
|
|
[(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
|
|
def ri_xor_r
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
|
|
[(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
|
|
|
|
def rr_and_not_r
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
|
|
def ri_and_not_r
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
|
|
def rr_or_not_r
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
|
|
def ri_or_not_r
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
|
|
def rr_xor_not_r
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), (not RegPred:$c)))]>;
|
|
def ri_xor_not_r
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp), (not RegPred:$c)))]>;
|
|
}
|
|
|
|
multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
|
|
CondCode ucmp, CondCode ocmp, string cmpstr> {
|
|
// TODO support 5-operand format: p|q, a, b, c
|
|
|
|
def rr_u
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
|
|
!strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
|
|
[(set RegPred:$p, (setcc RC:$a, RC:$b, ucmp))]>;
|
|
def rr_o
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b),
|
|
!strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
|
|
[(set RegPred:$p, (setcc RC:$a, RC:$b, ocmp))]>;
|
|
|
|
def rr_and_r_u
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, $c"),
|
|
[(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
|
|
def rr_and_r_o
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, $c"),
|
|
[(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
|
|
|
|
def rr_or_r_u
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, $c"),
|
|
[(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
|
|
def rr_or_r_o
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, $c"),
|
|
[(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
|
|
|
|
def rr_xor_r_u
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, $c"),
|
|
[(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp), RegPred:$c))]>;
|
|
def rr_xor_r_o
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, $c"),
|
|
[(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp), RegPred:$c))]>;
|
|
|
|
def rr_and_not_r_u
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, "u.and.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (and (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
|
|
def rr_and_not_r_o
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".and.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (and (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
|
|
|
|
def rr_or_not_r_u
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, "u.or.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (or (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
|
|
def rr_or_not_r_o
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".or.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (or (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
|
|
|
|
def rr_xor_not_r_u
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, "u.xor.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ucmp), (not RegPred:$c)))]>;
|
|
def rr_xor_not_r_o
|
|
: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
|
|
!strconcat("setp.", cmpstr, ".xor.", regclsname, "\t$p, $a, $b, !$c"),
|
|
[(set RegPred:$p, (xor (setcc RC:$a, RC:$b, ocmp), (not RegPred:$c)))]>;
|
|
}
|
|
|
|
multiclass PTX_SELP<RegisterClass RC, string regclsname> {
|
|
def rr
|
|
: InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, RC:$c),
|
|
!strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
|
|
[(set RC:$r, (select RegPred:$a, RC:$b, RC:$c))]>;
|
|
}
|
|
|
|
multiclass PTX_LD<string opstr, string typestr, RegisterClass RC, PatFrag pat_load> {
|
|
def rr32 : InstPTX<(outs RC:$d),
|
|
(ins MEMri32:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
|
|
[(set RC:$d, (pat_load ADDRrr32:$a))]>, Requires<[Use32BitAddresses]>;
|
|
def rr64 : InstPTX<(outs RC:$d),
|
|
(ins MEMri64:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
|
|
[(set RC:$d, (pat_load ADDRrr64:$a))]>, Requires<[Use64BitAddresses]>;
|
|
def ri32 : InstPTX<(outs RC:$d),
|
|
(ins MEMri32:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
|
|
[(set RC:$d, (pat_load ADDRri32:$a))]>, Requires<[Use32BitAddresses]>;
|
|
def ri64 : InstPTX<(outs RC:$d),
|
|
(ins MEMri64:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
|
|
[(set RC:$d, (pat_load ADDRri64:$a))]>, Requires<[Use64BitAddresses]>;
|
|
def ii32 : InstPTX<(outs RC:$d),
|
|
(ins MEMii32:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
|
|
[(set RC:$d, (pat_load ADDRii32:$a))]>, Requires<[Use32BitAddresses]>;
|
|
def ii64 : InstPTX<(outs RC:$d),
|
|
(ins MEMii64:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
|
|
[(set RC:$d, (pat_load ADDRii64:$a))]>, Requires<[Use64BitAddresses]>;
|
|
}
|
|
|
|
multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
|
|
defm u16 : PTX_LD<opstr, ".u16", RegI16, pat_load>;
|
|
defm u32 : PTX_LD<opstr, ".u32", RegI32, pat_load>;
|
|
defm u64 : PTX_LD<opstr, ".u64", RegI64, pat_load>;
|
|
defm f32 : PTX_LD<opstr, ".f32", RegF32, pat_load>;
|
|
defm f64 : PTX_LD<opstr, ".f64", RegF64, pat_load>;
|
|
}
|
|
|
|
multiclass PTX_ST<string opstr, string typestr, RegisterClass RC, PatFrag pat_store> {
|
|
def rr32 : InstPTX<(outs),
|
|
(ins RC:$d, MEMri32:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRrr32:$a)]>, Requires<[Use32BitAddresses]>;
|
|
def rr64 : InstPTX<(outs),
|
|
(ins RC:$d, MEMri64:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRrr64:$a)]>, Requires<[Use64BitAddresses]>;
|
|
def ri32 : InstPTX<(outs),
|
|
(ins RC:$d, MEMri32:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRri32:$a)]>, Requires<[Use32BitAddresses]>;
|
|
def ri64 : InstPTX<(outs),
|
|
(ins RC:$d, MEMri64:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRri64:$a)]>, Requires<[Use64BitAddresses]>;
|
|
def ii32 : InstPTX<(outs),
|
|
(ins RC:$d, MEMii32:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRii32:$a)]>, Requires<[Use32BitAddresses]>;
|
|
def ii64 : InstPTX<(outs),
|
|
(ins RC:$d, MEMii64:$a),
|
|
!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
|
|
[(pat_store RC:$d, ADDRii64:$a)]>, Requires<[Use64BitAddresses]>;
|
|
}
|
|
|
|
multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
|
|
defm u16 : PTX_ST<opstr, ".u16", RegI16, pat_store>;
|
|
defm u32 : PTX_ST<opstr, ".u32", RegI32, pat_store>;
|
|
defm u64 : PTX_ST<opstr, ".u64", RegI64, pat_store>;
|
|
defm f32 : PTX_ST<opstr, ".f32", RegF32, pat_store>;
|
|
defm f64 : PTX_ST<opstr, ".f64", RegF64, pat_store>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
///===- Integer Arithmetic Instructions -----------------------------------===//
|
|
|
|
defm ADD : INT3<"add", add>;
|
|
defm SUB : INT3<"sub", sub>;
|
|
defm MUL : INT3<"mul.lo", mul>; // FIXME: Allow 32x32 -> 64 multiplies
|
|
defm DIV : INT3<"div", udiv>;
|
|
defm REM : INT3<"rem", urem>;
|
|
|
|
///===- Floating-Point Arithmetic Instructions ----------------------------===//
|
|
|
|
// Standard Unary Operations
|
|
defm FNEG : PTX_FLOAT_2OP<"neg", fneg>;
|
|
|
|
// Standard Binary Operations
|
|
defm FADD : PTX_FLOAT_3OP<"add", fadd>;
|
|
defm FSUB : PTX_FLOAT_3OP<"sub", fsub>;
|
|
defm FMUL : PTX_FLOAT_3OP<"mul", fmul>;
|
|
|
|
// TODO: Allow user selection of rounding modes for fdiv.
|
|
// For division, we need to have f32 and f64 differently.
|
|
// For f32, we just always use .approx since it is supported on all hardware
|
|
// for PTX 1.4+, which is our minimum target.
|
|
def FDIVrr32 : InstPTX<(outs RegF32:$d),
|
|
(ins RegF32:$a, RegF32:$b),
|
|
"div.approx.f32\t$d, $a, $b",
|
|
[(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>;
|
|
def FDIVri32 : InstPTX<(outs RegF32:$d),
|
|
(ins RegF32:$a, f32imm:$b),
|
|
"div.approx.f32\t$d, $a, $b",
|
|
[(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>;
|
|
|
|
// For f64, we must specify a rounding for sm 1.3+ but *not* for sm 1.0.
|
|
def FDIVrr64SM13 : InstPTX<(outs RegF64:$d),
|
|
(ins RegF64:$a, RegF64:$b),
|
|
"div.rn.f64\t$d, $a, $b",
|
|
[(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
|
|
Requires<[SupportsSM13]>;
|
|
def FDIVri64SM13 : InstPTX<(outs RegF64:$d),
|
|
(ins RegF64:$a, f64imm:$b),
|
|
"div.rn.f64\t$d, $a, $b",
|
|
[(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
|
|
Requires<[SupportsSM13]>;
|
|
def FDIVrr64SM10 : InstPTX<(outs RegF64:$d),
|
|
(ins RegF64:$a, RegF64:$b),
|
|
"div.f64\t$d, $a, $b",
|
|
[(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
|
|
Requires<[DoesNotSupportSM13]>;
|
|
def FDIVri64SM10 : InstPTX<(outs RegF64:$d),
|
|
(ins RegF64:$a, f64imm:$b),
|
|
"div.f64\t$d, $a, $b",
|
|
[(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
|
|
Requires<[DoesNotSupportSM13]>;
|
|
|
|
|
|
|
|
// Multi-operation hybrid instructions
|
|
|
|
// The selection of mad/fma is tricky. In some cases, they are the *same*
|
|
// instruction, but in other cases we may prefer one or the other. Also,
|
|
// different PTX versions differ on whether rounding mode flags are required.
|
|
// In the short term, mad is supported on all PTX versions and we use a
|
|
// default rounding mode no matter what shader model or PTX version.
|
|
// TODO: Allow the rounding mode to be selectable through llc.
|
|
defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>, Requires<[SupportsSM13, SupportsFMA]>;
|
|
defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>, Requires<[DoesNotSupportSM13, SupportsFMA]>;
|
|
|
|
///===- Floating-Point Intrinsic Instructions -----------------------------===//
|
|
|
|
def FSQRT32 : InstPTX<(outs RegF32:$d),
|
|
(ins RegF32:$a),
|
|
"sqrt.rn.f32\t$d, $a",
|
|
[(set RegF32:$d, (fsqrt RegF32:$a))]>;
|
|
|
|
def FSQRT64 : InstPTX<(outs RegF64:$d),
|
|
(ins RegF64:$a),
|
|
"sqrt.rn.f64\t$d, $a",
|
|
[(set RegF64:$d, (fsqrt RegF64:$a))]>;
|
|
|
|
def FSIN32 : InstPTX<(outs RegF32:$d),
|
|
(ins RegF32:$a),
|
|
"sin.approx.f32\t$d, $a",
|
|
[(set RegF32:$d, (fsin RegF32:$a))]>;
|
|
|
|
def FSIN64 : InstPTX<(outs RegF64:$d),
|
|
(ins RegF64:$a),
|
|
"sin.approx.f64\t$d, $a",
|
|
[(set RegF64:$d, (fsin RegF64:$a))]>;
|
|
|
|
def FCOS32 : InstPTX<(outs RegF32:$d),
|
|
(ins RegF32:$a),
|
|
"cos.approx.f32\t$d, $a",
|
|
[(set RegF32:$d, (fcos RegF32:$a))]>;
|
|
|
|
def FCOS64 : InstPTX<(outs RegF64:$d),
|
|
(ins RegF64:$a),
|
|
"cos.approx.f64\t$d, $a",
|
|
[(set RegF64:$d, (fcos RegF64:$a))]>;
|
|
|
|
|
|
///===- Comparison and Selection Instructions -----------------------------===//
|
|
|
|
// .setp
|
|
|
|
// Compare u16
|
|
|
|
defm SETPEQu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETEQ, "eq">;
|
|
defm SETPNEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETNE, "ne">;
|
|
defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">;
|
|
defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">;
|
|
defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">;
|
|
defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">;
|
|
|
|
// Compare u32
|
|
|
|
defm SETPEQu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETEQ, "eq">;
|
|
defm SETPNEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETNE, "ne">;
|
|
defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">;
|
|
defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">;
|
|
defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">;
|
|
defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">;
|
|
|
|
// Compare u64
|
|
|
|
defm SETPEQu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETEQ, "eq">;
|
|
defm SETPNEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETNE, "ne">;
|
|
defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">;
|
|
defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">;
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defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">;
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defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">;
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// Compare f32
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defm SETPEQf32 : PTX_SETP_FP<RegF32, "f32", SETUEQ, SETOEQ, "eq">;
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defm SETPNEf32 : PTX_SETP_FP<RegF32, "f32", SETUNE, SETONE, "ne">;
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defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", SETULT, SETOLT, "lt">;
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defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", SETULE, SETOLE, "le">;
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defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", SETUGT, SETOGT, "gt">;
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defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", SETUGE, SETOGE, "ge">;
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// Compare f64
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defm SETPEQf64 : PTX_SETP_FP<RegF64, "f64", SETUEQ, SETOEQ, "eq">;
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defm SETPNEf64 : PTX_SETP_FP<RegF64, "f64", SETUNE, SETONE, "ne">;
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defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", SETULT, SETOLT, "lt">;
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defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", SETULE, SETOLE, "le">;
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defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", SETUGT, SETOGT, "gt">;
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defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", SETUGE, SETOGE, "ge">;
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// .selp
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defm PTX_SELPu16 : PTX_SELP<RegI16, "u16">;
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defm PTX_SELPu32 : PTX_SELP<RegI32, "u32">;
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defm PTX_SELPu64 : PTX_SELP<RegI64, "u64">;
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defm PTX_SELPf32 : PTX_SELP<RegF32, "f32">;
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defm PTX_SELPf64 : PTX_SELP<RegF64, "f64">;
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///===- Logic and Shift Instructions --------------------------------------===//
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defm SHL : INT3ntnc<"shl.b", PTXshl>;
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defm SRL : INT3ntnc<"shr.u", PTXsrl>;
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defm SRA : INT3ntnc<"shr.s", PTXsra>;
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defm AND : PTX_LOGIC<"and", and>;
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defm OR : PTX_LOGIC<"or", or>;
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defm XOR : PTX_LOGIC<"xor", xor>;
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///===- Data Movement and Conversion Instructions -------------------------===//
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let neverHasSideEffects = 1 in {
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def MOVPREDrr
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: InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
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def MOVU16rr
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: InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
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def MOVU32rr
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: InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
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def MOVU64rr
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: InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
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def MOVF32rr
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: InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
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def MOVF64rr
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: InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
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}
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOVPREDri
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: InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
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[(set RegPred:$d, imm:$a)]>;
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def MOVU16ri
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: InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
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[(set RegI16:$d, imm:$a)]>;
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def MOVU32ri
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: InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
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[(set RegI32:$d, imm:$a)]>;
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def MOVU64ri
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: InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
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[(set RegI64:$d, imm:$a)]>;
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def MOVF32ri
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: InstPTX<(outs RegF32:$d), (ins f32imm:$a), "mov.f32\t$d, $a",
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[(set RegF32:$d, fpimm:$a)]>;
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def MOVF64ri
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: InstPTX<(outs RegF64:$d), (ins f64imm:$a), "mov.f64\t$d, $a",
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[(set RegF64:$d, fpimm:$a)]>;
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}
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOVaddr32
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: InstPTX<(outs RegI32:$d), (ins i32imm:$a), "mov.u32\t$d, $a",
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[(set RegI32:$d, (PTXcopyaddress tglobaladdr:$a))]>;
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def MOVaddr64
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: InstPTX<(outs RegI64:$d), (ins i64imm:$a), "mov.u64\t$d, $a",
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[(set RegI64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
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}
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// Loads
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defm LDg : PTX_LD_ALL<"ld.global", load_global>;
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defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
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defm LDl : PTX_LD_ALL<"ld.local", load_local>;
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defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
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|
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// This is a special instruction that is manually inserted for kernel parameters
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def LDpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
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"ld.param.u16\t$d, [$a]", []>;
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def LDpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a),
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|
"ld.param.u32\t$d, [$a]", []>;
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def LDpiU64 : InstPTX<(outs RegI64:$d), (ins MEMpi:$a),
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|
"ld.param.u64\t$d, [$a]", []>;
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def LDpiF32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a),
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|
"ld.param.f32\t$d, [$a]", []>;
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def LDpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a),
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|
"ld.param.f64\t$d, [$a]", []>;
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|
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// Stores
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defm STg : PTX_ST_ALL<"st.global", store_global>;
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defm STl : PTX_ST_ALL<"st.local", store_local>;
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defm STs : PTX_ST_ALL<"st.shared", store_shared>;
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// defm STp : PTX_ST_ALL<"st.param", store_parameter>;
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// defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
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// TODO: Do something with st.param if/when it is needed.
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|
|
// Conversion to pred
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|
|
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def CVT_pred_u16
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|
: InstPTX<(outs RegPred:$d), (ins RegI16:$a), "cvt.pred.u16\t$d, $a",
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|
[(set RegPred:$d, (trunc RegI16:$a))]>;
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def CVT_pred_u32
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|
: InstPTX<(outs RegPred:$d), (ins RegI32:$a), "cvt.pred.u32\t$d, $a",
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[(set RegPred:$d, (trunc RegI32:$a))]>;
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|
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def CVT_pred_u64
|
|
: InstPTX<(outs RegPred:$d), (ins RegI64:$a), "cvt.pred.u64\t$d, $a",
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[(set RegPred:$d, (trunc RegI64:$a))]>;
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|
|
def CVT_pred_f32
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|
: InstPTX<(outs RegPred:$d), (ins RegF32:$a), "cvt.rni.pred.f32\t$d, $a",
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|
[(set RegPred:$d, (fp_to_uint RegF32:$a))]>;
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|
|
|
def CVT_pred_f64
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|
: InstPTX<(outs RegPred:$d), (ins RegF64:$a), "cvt.rni.pred.f64\t$d, $a",
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|
[(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
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|
|
|
// Conversion to u16
|
|
|
|
def CVT_u16_pred
|
|
: InstPTX<(outs RegI16:$d), (ins RegPred:$a), "cvt.u16.pred\t$d, $a",
|
|
[(set RegI16:$d, (zext RegPred:$a))]>;
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|
|
|
def CVT_u16_u32
|
|
: InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a",
|
|
[(set RegI16:$d, (trunc RegI32:$a))]>;
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|
|
|
def CVT_u16_u64
|
|
: InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a",
|
|
[(set RegI16:$d, (trunc RegI64:$a))]>;
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|
|
|
def CVT_u16_f32
|
|
: InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rni.u16.f32\t$d, $a",
|
|
[(set RegI16:$d, (fp_to_uint RegF32:$a))]>;
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|
|
|
def CVT_u16_f64
|
|
: InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rni.u16.f64\t$d, $a",
|
|
[(set RegI16:$d, (fp_to_uint RegF64:$a))]>;
|
|
|
|
// Conversion to u32
|
|
|
|
def CVT_u32_pred
|
|
: InstPTX<(outs RegI32:$d), (ins RegPred:$a), "cvt.u32.pred\t$d, $a",
|
|
[(set RegI32:$d, (zext RegPred:$a))]>;
|
|
|
|
def CVT_u32_u16
|
|
: InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
|
|
[(set RegI32:$d, (zext RegI16:$a))]>;
|
|
|
|
def CVT_u32_u64
|
|
: InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a",
|
|
[(set RegI32:$d, (trunc RegI64:$a))]>;
|
|
|
|
def CVT_u32_f32
|
|
: InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rni.u32.f32\t$d, $a",
|
|
[(set RegI32:$d, (fp_to_uint RegF32:$a))]>;
|
|
|
|
def CVT_u32_f64
|
|
: InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rni.u32.f64\t$d, $a",
|
|
[(set RegI32:$d, (fp_to_uint RegF64:$a))]>;
|
|
|
|
// Conversion to u64
|
|
|
|
def CVT_u64_pred
|
|
: InstPTX<(outs RegI64:$d), (ins RegPred:$a), "cvt.u64.pred\t$d, $a",
|
|
[(set RegI64:$d, (zext RegPred:$a))]>;
|
|
|
|
def CVT_u64_u16
|
|
: InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
|
|
[(set RegI64:$d, (zext RegI16:$a))]>;
|
|
|
|
def CVT_u64_u32
|
|
: InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
|
|
[(set RegI64:$d, (zext RegI32:$a))]>;
|
|
|
|
def CVT_u64_f32
|
|
: InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rni.u64.f32\t$d, $a",
|
|
[(set RegI64:$d, (fp_to_uint RegF32:$a))]>;
|
|
|
|
def CVT_u64_f64
|
|
: InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rni.u64.f64\t$d, $a",
|
|
[(set RegI64:$d, (fp_to_uint RegF64:$a))]>;
|
|
|
|
// Conversion to f32
|
|
|
|
def CVT_f32_pred
|
|
: InstPTX<(outs RegF32:$d), (ins RegPred:$a), "cvt.rn.f32.pred\t$d, $a",
|
|
[(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
|
|
|
|
def CVT_f32_u16
|
|
: InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a",
|
|
[(set RegF32:$d, (uint_to_fp RegI16:$a))]>;
|
|
|
|
def CVT_f32_u32
|
|
: InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.u32\t$d, $a",
|
|
[(set RegF32:$d, (uint_to_fp RegI32:$a))]>;
|
|
|
|
def CVT_f32_u64
|
|
: InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.u64\t$d, $a",
|
|
[(set RegF32:$d, (uint_to_fp RegI64:$a))]>;
|
|
|
|
def CVT_f32_f64
|
|
: InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a",
|
|
[(set RegF32:$d, (fround RegF64:$a))]>;
|
|
|
|
// Conversion to f64
|
|
|
|
def CVT_f64_pred
|
|
: InstPTX<(outs RegF64:$d), (ins RegPred:$a), "cvt.rn.f64.pred\t$d, $a",
|
|
[(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
|
|
|
|
def CVT_f64_u16
|
|
: InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a",
|
|
[(set RegF64:$d, (uint_to_fp RegI16:$a))]>;
|
|
|
|
def CVT_f64_u32
|
|
: InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.u32\t$d, $a",
|
|
[(set RegF64:$d, (uint_to_fp RegI32:$a))]>;
|
|
|
|
def CVT_f64_u64
|
|
: InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.u64\t$d, $a",
|
|
[(set RegF64:$d, (uint_to_fp RegI64:$a))]>;
|
|
|
|
def CVT_f64_f32
|
|
: InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a",
|
|
[(set RegF64:$d, (fextend RegF32:$a))]>;
|
|
|
|
///===- Control Flow Instructions -----------------------------------------===//
|
|
|
|
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
|
|
def BRAd
|
|
: InstPTX<(outs), (ins brtarget:$d), "bra\t$d", [(br bb:$d)]>;
|
|
}
|
|
|
|
let isBranch = 1, isTerminator = 1 in {
|
|
// FIXME: The pattern part is blank because I cannot (or do not yet know
|
|
// how to) use the first operand of PredicateOperand (a RegPred register) here
|
|
def BRAdp
|
|
: InstPTX<(outs), (ins brtarget:$d), "bra\t$d",
|
|
[/*(brcond pred:$_p, bb:$d)*/]>;
|
|
}
|
|
|
|
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
|
|
def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
|
|
def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
|
|
}
|
|
|
|
///===- Intrinsic Instructions --------------------------------------------===//
|
|
|
|
include "PTXIntrinsicInstrInfo.td"
|