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https://github.com/RPCSX/llvm.git
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d2c33c4ecb
Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287162 91177308-0d34-0410-b5e6-96231b3b80d8
143 lines
2.8 KiB
LLVM
143 lines
2.8 KiB
LLVM
; RUN: llc -mattr=avr6,sram < %s -march=avr | FileCheck %s
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;TODO: test returning byval structs
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; TODO: test naked functions
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define void @return_void() {
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; CHECK: return_void:{{[a-zA-Z0-9 #@]*}}
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; CHECK-NEXT: #{{[a-zA-Z0-9 #@]*}}
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; CHECK-NEXT: ret
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ret void
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}
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define i8 @return8_imm() {
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; CHECK-LABEL: return8_imm:
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; CHECK: ldi r24, 5
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ret i8 5
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}
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define i8 @return8_arg(i8 %x) {
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; CHECK: return8_arg:{{[a-zA-Z0-9 #@]*}}
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; CHECK-NEXT: #{{[a-zA-Z0-9 #@]*}}
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; CHECK-NEXT: ret
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ret i8 %x
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}
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define i8 @return8_arg2(i8 %x, i8 %y, i8 %z) {
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; CHECK-LABEL: return8_arg2:
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; CHECK: mov r24, r20
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ret i8 %z
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}
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define i16 @return16_imm() {
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; CHECK-LABEL: return16_imm:
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; CHECK: ldi r24, 57
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; CHECK: ldi r25, 48
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ret i16 12345
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}
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define i16 @return16_arg(i16 %x) {
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; CHECK: return16_arg:{{[a-zA-Z0-9 #@]*}}
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; CHECK-NEXT: #{{[a-zA-Z0-9 #@]*}}
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; CHECK-NEXT: ret
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ret i16 %x
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}
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define i16 @return16_arg2(i16 %x, i16 %y, i16 %z) {
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; CHECK-LABEL: return16_arg2:
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; CHECK: movw r24, r20
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ret i16 %z
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}
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define i32 @return32_imm() {
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; CHECK-LABEL: return32_imm:
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; CHECK: ldi r22, 21
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; CHECK: ldi r23, 205
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; CHECK: ldi r24, 91
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; CHECK: ldi r25, 7
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ret i32 123456789
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}
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define i32 @return32_arg(i32 %x) {
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; CHECK: return32_arg:{{[a-zA-Z0-9 #@]*}}
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; CHECK-NEXT: #{{[a-zA-Z0-9 #@]*}}
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; CHECK-NEXT: ret
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ret i32 %x
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}
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define i32 @return32_arg2(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: return32_arg2:
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; CHECK: movw r22, r14
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; CHECK: movw r24, r16
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ret i32 %z
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}
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define i64 @return64_imm() {
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; CHECK-LABEL: return64_imm:
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; CHECK: ldi r18, 204
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; CHECK: ldi r19, 204
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; CHECK: ldi r20, 104
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; CHECK: ldi r21, 37
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; CHECK: ldi r22, 25
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; CHECK: ldi r23, 22
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; CHECK: ldi r24, 236
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; CHECK: ldi r25, 190
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ret i64 13757395258967641292
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}
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define i64 @return64_arg(i64 %x) {
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; CHECK: return64_arg:{{[a-zA-Z0-9 #@]*}}
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; CHECK-NEXT: #{{[a-zA-Z0-9 #@]*}}
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; CHECK-NEXT: ret
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ret i64 %x
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}
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define i64 @return64_arg2(i64 %x, i64 %y, i64 %z) {
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; CHECK-LABEL: return64_arg2:
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; CHECK: push r28
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; CHECK: push r29
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; CHECK: ldd r18, Y+5
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; CHECK: ldd r19, Y+6
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; CHECK: ldd r20, Y+7
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; CHECK: ldd r21, Y+8
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; CHECK: ldd r22, Y+9
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; CHECK: ldd r23, Y+10
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; CHECK: ldd r24, Y+11
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; CHECK: ldd r25, Y+12
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; CHECK: pop r29
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; CHECK: pop r28
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ret i64 %z
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}
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define i32 @return64_trunc(i32 %a, i32 %b, i32 %c, i64 %d) {
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; CHECK-LABEL: return64_trunc:
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; CHECK: push r28
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; CHECK: push r29
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; CHECK: ldd r22, Y+5
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; CHECK: ldd r23, Y+6
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; CHECK: ldd r24, Y+7
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; CHECK: ldd r25, Y+8
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; CHECK: pop r29
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; CHECK: pop r28
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%result = trunc i64 %d to i32
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ret i32 %result
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}
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define i32 @naked(i32 %x) naked {
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; CHECK-LABEL: naked:
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; CHECK-NOT: ret
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ret i32 %x
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}
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define avr_intrcc void @interrupt_handler() {
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; CHECK-LABEL: interrupt_handler:
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; CHECK: reti
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ret void
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}
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define avr_signalcc void @signal_handler() {
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; CHECK-LABEL: signal_handler:
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; CHECK: reti
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ret void
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}
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