llvm/utils/TableGen/CMakeLists.txt
Jim Grosbach 86f9adb8be TableGen'erated MC lowering for simple pseudo-instructions.
This allows the (many) pseudo-instructions we have that map onto a single
real instruction to have their expansion during MC lowering handled
automatically instead of the current cumbersome manual expansion required.
These sorts of pseudos are common when an instruction is used in situations
that require different MachineInstr flags (isTerminator, isBranch, et. al.)
than the generic instruction description has. For example, using a move
to the PC to implement a branch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 17:36:35 +00:00

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1.4 KiB
CMake

set(LLVM_REQUIRES_EH 1)
set(LLVM_REQUIRES_RTTI 1)
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_TOOLS_BINARY_DIR})
add_llvm_utility(tblgen
ARMDecoderEmitter.cpp
AsmMatcherEmitter.cpp
AsmWriterEmitter.cpp
AsmWriterInst.cpp
CallingConvEmitter.cpp
ClangASTNodesEmitter.cpp
ClangAttrEmitter.cpp
ClangDiagnosticsEmitter.cpp
ClangSACheckersEmitter.cpp
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp
CodeGenInstruction.cpp
CodeGenRegisters.cpp
CodeGenTarget.cpp
DAGISelEmitter.cpp
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp
DAGISelMatcherOpt.cpp
DAGISelMatcher.cpp
DisassemblerEmitter.cpp
EDEmitter.cpp
Error.cpp
FastISelEmitter.cpp
FixedLenDecoderEmitter.cpp
InstrEnumEmitter.cpp
InstrInfoEmitter.cpp
IntrinsicEmitter.cpp
LLVMCConfigurationEmitter.cpp
NeonEmitter.cpp
OptParserEmitter.cpp
PseudoLoweringEmitter.cpp
Record.cpp
RegisterInfoEmitter.cpp
SetTheory.cpp
StringMatcher.cpp
SubtargetEmitter.cpp
TGLexer.cpp
TGParser.cpp
TGValueTypes.cpp
TableGen.cpp
TableGenBackend.cpp
X86DisassemblerTables.cpp
X86RecognizableInstr.cpp
)
target_link_libraries(tblgen LLVMSupport)
if( MINGW )
target_link_libraries(tblgen imagehlp psapi)
endif( MINGW )
if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD AND NOT BEOS )
target_link_libraries(tblgen pthread)
endif()
install(TARGETS tblgen RUNTIME DESTINATION bin)