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ea7a0c0467
This makes it possible to distinguish between mesa shaders and other kernels even in the presence of compute shaders. Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Differential Revision: http://reviews.llvm.org/D18559 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265589 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
1.3 KiB
LLVM
30 lines
1.3 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK-NOT: MOV
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define amdgpu_vs void @test(<4 x float> inreg %reg0) {
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%1 = extractelement <4 x float> %reg0, i32 0
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%2 = extractelement <4 x float> %reg0, i32 1
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%3 = extractelement <4 x float> %reg0, i32 2
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%4 = extractelement <4 x float> %reg0, i32 3
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%5 = fmul float %1, 3.0
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%6 = fmul float %2, 3.0
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%7 = fmul float %3, 3.0
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%8 = fmul float %4, 3.0
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%9 = insertelement <4 x float> undef, float %5, i32 0
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%10 = insertelement <4 x float> %9, float %6, i32 1
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%11 = insertelement <4 x float> undef, float %7, i32 0
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%12 = insertelement <4 x float> %11, float %5, i32 1
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%13 = insertelement <4 x float> undef, float %8, i32 0
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%14 = call <4 x float> @llvm.r600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%15 = call <4 x float> @llvm.r600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%16 = call <4 x float> @llvm.r600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%17 = fadd <4 x float> %14, %15
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%18 = fadd <4 x float> %17, %16
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call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0)
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ret void
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}
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declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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