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5255fef87c
SI_MASKED_UNREACHABLE does not have machine instruction encoding. It needs special handling in AMDGPUAsmPrinter::EmitInstruction like some other pseudo instructions. This patch fixes compilation failure of RadeonRays. Differential Revision: https://reviews.llvm.org/D32364 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301025 91177308-0d34-0410-b5e6-96231b3b80d8
272 lines
9.3 KiB
C++
272 lines
9.3 KiB
C++
//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPUMCInstLower.h"
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#include "AMDGPUAsmPrinter.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDGPUTargetMachine.h"
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#include "InstPrinter/AMDGPUInstPrinter.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCObjectStreamer.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include <algorithm>
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using namespace llvm;
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#include "AMDGPUGenMCPseudoLowering.inc"
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AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st,
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const AsmPrinter &ap):
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Ctx(ctx), ST(st), AP(ap) { }
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static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
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switch (MOFlags) {
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default:
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return MCSymbolRefExpr::VK_None;
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case SIInstrInfo::MO_GOTPCREL:
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return MCSymbolRefExpr::VK_GOTPCREL;
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case SIInstrInfo::MO_GOTPCREL32_LO:
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return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
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case SIInstrInfo::MO_GOTPCREL32_HI:
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return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
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case SIInstrInfo::MO_REL32_LO:
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return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
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case SIInstrInfo::MO_REL32_HI:
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return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
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}
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}
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const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
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const MachineBasicBlock &SrcBB,
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const MachineOperand &MO) const {
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const MCExpr *DestBBSym
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= MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx);
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const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
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assert(SrcBB.front().getOpcode() == AMDGPU::S_GETPC_B64 &&
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ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
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// s_getpc_b64 returns the address of next instruction.
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const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
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SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
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if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD)
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return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
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assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD);
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return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
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}
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bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
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MCOperand &MCOp) const {
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switch (MO.getType()) {
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default:
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::createImm(MO.getImm());
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return true;
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case MachineOperand::MO_Register:
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MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
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return true;
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case MachineOperand::MO_MachineBasicBlock: {
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if (MO.getTargetFlags() != 0) {
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MCOp = MCOperand::createExpr(
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getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
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} else {
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MCOp = MCOperand::createExpr(
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MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
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}
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return true;
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}
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case MachineOperand::MO_GlobalAddress: {
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const GlobalValue *GV = MO.getGlobal();
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SmallString<128> SymbolName;
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AP.getNameWithPrefix(SymbolName, GV);
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MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
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const MCExpr *SymExpr =
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MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
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const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
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MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
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MCOp = MCOperand::createExpr(Expr);
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return true;
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}
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case MachineOperand::MO_ExternalSymbol: {
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MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
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Sym->setExternal(true);
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const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
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MCOp = MCOperand::createExpr(Expr);
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return true;
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}
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}
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}
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void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
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int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode());
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if (MCOpcode == -1) {
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LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
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C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
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"a target-specific version: " + Twine(MI->getOpcode()));
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}
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OutMI.setOpcode(MCOpcode);
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for (const MachineOperand &MO : MI->explicit_operands()) {
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MCOperand MCOp;
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lowerOperand(MO, MCOp);
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OutMI.addOperand(MCOp);
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}
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}
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bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
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MCOperand &MCOp) const {
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const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
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AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
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return MCInstLowering.lowerOperand(MO, MCOp);
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}
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const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) {
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// TargetMachine does not support llvm-style cast. Use C++-style cast.
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// This is safe since TM is always of type AMDGPUTargetMachine or its
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// derived class.
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auto *AT = static_cast<AMDGPUTargetMachine*>(&TM);
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auto *CE = dyn_cast<ConstantExpr>(CV);
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// Lower null pointers in private and local address space.
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// Clang generates addrspacecast for null pointers in private and local
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// address space, which needs to be lowered.
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if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
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auto Op = CE->getOperand(0);
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auto SrcAddr = Op->getType()->getPointerAddressSpace();
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if (Op->isNullValue() && AT->getNullPointerValue(SrcAddr) == 0) {
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auto DstAddr = CE->getType()->getPointerAddressSpace();
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return MCConstantExpr::create(AT->getNullPointerValue(DstAddr),
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OutContext);
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}
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}
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return AsmPrinter::lowerConstant(CV);
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}
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void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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if (emitPseudoExpansionLowering(*OutStreamer, MI))
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return;
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const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
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AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
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StringRef Err;
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if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
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LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
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C.emitError("Illegal instruction detected: " + Err);
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MI->print(errs());
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}
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if (MI->isBundle()) {
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const MachineBasicBlock *MBB = MI->getParent();
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MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
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while (I != MBB->instr_end() && I->isInsideBundle()) {
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EmitInstruction(&*I);
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++I;
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}
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} else {
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// We don't want SI_MASK_BRANCH/SI_RETURN_TO_EPILOG encoded. They are
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// placeholder terminator instructions and should only be printed as
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// comments.
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if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
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if (isVerbose()) {
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SmallVector<char, 16> BBStr;
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raw_svector_ostream Str(BBStr);
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const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
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const MCSymbolRefExpr *Expr
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= MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
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Expr->print(Str, MAI);
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OutStreamer->emitRawComment(" mask branch " + BBStr);
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}
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return;
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}
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if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
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if (isVerbose())
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OutStreamer->emitRawComment(" return to shader part epilog");
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return;
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}
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if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
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if (isVerbose())
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OutStreamer->emitRawComment(" wave barrier");
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return;
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}
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if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
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if (isVerbose())
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OutStreamer->emitRawComment(" divergent unreachable");
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return;
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}
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MCInst TmpInst;
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MCInstLowering.lower(MI, TmpInst);
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EmitToStreamer(*OutStreamer, TmpInst);
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if (STI.dumpCode()) {
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// Disassemble instruction/operands to text.
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DisasmLines.resize(DisasmLines.size() + 1);
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std::string &DisasmLine = DisasmLines.back();
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raw_string_ostream DisasmStream(DisasmLine);
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AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
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*STI.getInstrInfo(),
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*STI.getRegisterInfo());
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InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
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// Disassemble instruction/operands to hex representation.
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SmallVector<MCFixup, 4> Fixups;
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SmallVector<char, 16> CodeBytes;
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raw_svector_ostream CodeStream(CodeBytes);
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auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
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MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
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InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
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MF->getSubtarget<MCSubtargetInfo>());
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HexLines.resize(HexLines.size() + 1);
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std::string &HexLine = HexLines.back();
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raw_string_ostream HexStream(HexLine);
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for (size_t i = 0; i < CodeBytes.size(); i += 4) {
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unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
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HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
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}
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DisasmStream.flush();
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DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
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}
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}
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}
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