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ae5f5d3d3c
This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283702 91177308-0d34-0410-b5e6-96231b3b80d8
244 lines
8.1 KiB
C++
244 lines
8.1 KiB
C++
//===-- LanaiAsmPrinter.cpp - Lanai LLVM assembly writer ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to the Lanai assembly language.
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//
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//===----------------------------------------------------------------------===//
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#include "InstPrinter/LanaiInstPrinter.h"
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#include "Lanai.h"
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#include "LanaiInstrInfo.h"
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#include "LanaiMCInstLower.h"
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#include "LanaiTargetMachine.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Mangler.h"
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#include "llvm/IR/Module.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "asm-printer"
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using namespace llvm;
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namespace {
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class LanaiAsmPrinter : public AsmPrinter {
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public:
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explicit LanaiAsmPrinter(TargetMachine &TM,
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std::unique_ptr<MCStreamer> Streamer)
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: AsmPrinter(TM, std::move(Streamer)) {}
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StringRef getPassName() const override { return "Lanai Assembly Printer"; }
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void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O) override;
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void EmitInstruction(const MachineInstr *MI) override;
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bool isBlockOnlyReachableByFallthrough(
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const MachineBasicBlock *MBB) const override;
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private:
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void customEmitInstruction(const MachineInstr *MI);
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void emitCallInstruction(const MachineInstr *MI);
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};
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} // end of anonymous namespace
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void LanaiAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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switch (MO.getType()) {
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case MachineOperand::MO_Register:
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O << LanaiInstPrinter::getRegisterName(MO.getReg());
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break;
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case MachineOperand::MO_Immediate:
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O << MO.getImm();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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break;
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case MachineOperand::MO_GlobalAddress:
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O << *getSymbol(MO.getGlobal());
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break;
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case MachineOperand::MO_BlockAddress: {
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MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
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O << BA->getName();
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break;
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}
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case MachineOperand::MO_ExternalSymbol:
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O << *GetExternalSymbolSymbol(MO.getSymbolName());
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break;
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case MachineOperand::MO_JumpTableIndex:
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O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_'
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<< MO.getIndex();
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_'
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<< MO.getIndex();
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return;
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default:
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llvm_unreachable("<unknown operand type>");
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}
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}
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// PrintAsmOperand - Print out an operand for an inline asm expression.
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bool LanaiAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned /*AsmVariant*/,
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const char *ExtraCode, raw_ostream &O) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1])
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return true; // Unknown modifier.
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switch (ExtraCode[0]) {
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// The highest-numbered register of a pair.
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case 'H': {
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if (OpNo == 0)
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return true;
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const MachineOperand &FlagsOP = MI->getOperand(OpNo - 1);
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if (!FlagsOP.isImm())
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return true;
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unsigned Flags = FlagsOP.getImm();
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unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
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if (NumVals != 2)
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return true;
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unsigned RegOp = OpNo + 1;
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if (RegOp >= MI->getNumOperands())
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return true;
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const MachineOperand &MO = MI->getOperand(RegOp);
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if (!MO.isReg())
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return true;
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unsigned Reg = MO.getReg();
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O << LanaiInstPrinter::getRegisterName(Reg);
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return false;
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}
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default:
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return true; // Unknown modifier.
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}
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}
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printOperand(MI, OpNo, O);
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return false;
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}
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//===----------------------------------------------------------------------===//
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void LanaiAsmPrinter::emitCallInstruction(const MachineInstr *MI) {
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assert((MI->getOpcode() == Lanai::CALL || MI->getOpcode() == Lanai::CALLR) &&
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"Unsupported call function");
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LanaiMCInstLower MCInstLowering(OutContext, *this);
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MCSubtargetInfo STI = getSubtargetInfo();
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// Insert save rca instruction immediately before the call.
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// TODO: We should generate a pc-relative mov instruction here instead
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// of pc + 16 (should be mov .+16 %rca).
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OutStreamer->EmitInstruction(MCInstBuilder(Lanai::ADD_I_LO)
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.addReg(Lanai::RCA)
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.addReg(Lanai::PC)
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.addImm(16),
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STI);
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// Push rca onto the stack.
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// st %rca, [--%sp]
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OutStreamer->EmitInstruction(MCInstBuilder(Lanai::SW_RI)
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.addReg(Lanai::RCA)
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.addReg(Lanai::SP)
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.addImm(-4)
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.addImm(LPAC::makePreOp(LPAC::ADD)),
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STI);
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// Lower the call instruction.
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if (MI->getOpcode() == Lanai::CALL) {
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MCInst TmpInst;
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MCInstLowering.Lower(MI, TmpInst);
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TmpInst.setOpcode(Lanai::BT);
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OutStreamer->EmitInstruction(TmpInst, STI);
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} else {
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OutStreamer->EmitInstruction(MCInstBuilder(Lanai::ADD_R)
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.addReg(Lanai::PC)
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.addReg(MI->getOperand(0).getReg())
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.addReg(Lanai::R0)
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.addImm(LPCC::ICC_T),
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STI);
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}
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}
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void LanaiAsmPrinter::customEmitInstruction(const MachineInstr *MI) {
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LanaiMCInstLower MCInstLowering(OutContext, *this);
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MCSubtargetInfo STI = getSubtargetInfo();
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MCInst TmpInst;
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MCInstLowering.Lower(MI, TmpInst);
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OutStreamer->EmitInstruction(TmpInst, STI);
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}
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void LanaiAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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MachineBasicBlock::const_instr_iterator I = MI->getIterator();
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MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
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do {
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if (I->isCall()) {
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emitCallInstruction(&*I);
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continue;
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}
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customEmitInstruction(&*I);
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} while ((++I != E) && I->isInsideBundle());
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}
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// isBlockOnlyReachableByFallthough - Return true if the basic block has
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// exactly one predecessor and the control transfer mechanism between
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// the predecessor and this block is a fall-through.
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// FIXME: could the overridden cases be handled in AnalyzeBranch?
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bool LanaiAsmPrinter::isBlockOnlyReachableByFallthrough(
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const MachineBasicBlock *MBB) const {
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// The predecessor has to be immediately before this block.
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const MachineBasicBlock *Pred = *MBB->pred_begin();
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// If the predecessor is a switch statement, assume a jump table
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// implementation, so it is not a fall through.
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if (const BasicBlock *B = Pred->getBasicBlock())
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if (isa<SwitchInst>(B->getTerminator()))
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return false;
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// Check default implementation
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if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
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return false;
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// Otherwise, check the last instruction.
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// Check if the last terminator is an unconditional branch.
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MachineBasicBlock::const_iterator I = Pred->end();
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while (I != Pred->begin() && !(--I)->isTerminator()) {
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}
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return !I->isBarrier();
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}
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// Force static initialization.
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extern "C" void LLVMInitializeLanaiAsmPrinter() {
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RegisterAsmPrinter<LanaiAsmPrinter> X(getTheLanaiTarget());
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}
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