llvm/test/CodeGen/ARM/sbfx.ll
Chris Lattner efcddc3325 add a simple dag combine to replace trivial shl+lshr with
and.  This happens with the store->load narrowing stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 05:28:43 +00:00

48 lines
807 B
LLVM

; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
define i32 @f1(i32 %a) {
entry:
; CHECK: f1:
; CHECK: sbfx r0, r0, #0, #20
%tmp = shl i32 %a, 12
%tmp2 = ashr i32 %tmp, 12
ret i32 %tmp2
}
define i32 @f2(i32 %a) {
entry:
; CHECK: f2:
; CHECK: bfc r0, #20, #12
%tmp = shl i32 %a, 12
%tmp2 = lshr i32 %tmp, 12
ret i32 %tmp2
}
define i32 @f3(i32 %a) {
entry:
; CHECK: f3:
; CHECK: sbfx r0, r0, #5, #3
%tmp = shl i32 %a, 24
%tmp2 = ashr i32 %tmp, 29
ret i32 %tmp2
}
define i32 @f4(i32 %a) {
entry:
; CHECK: f4:
; CHECK: ubfx r0, r0, #5, #3
%tmp = shl i32 %a, 24
%tmp2 = lshr i32 %tmp, 29
ret i32 %tmp2
}
define i32 @f5(i32 %a) {
entry:
; CHECK: f5:
; CHECK-NOT: sbfx
; CHECK: bx
%tmp = shl i32 %a, 3
%tmp2 = ashr i32 %tmp, 1
ret i32 %tmp2
}