| .. |
|
AsmParser
|
[Hexagon] Define certain aliases for vector instructions
|
2016-04-28 16:43:16 +00:00 |
|
Disassembler
|
|
|
|
MCTargetDesc
|
Fix -Wunused-variable in non-Asserts build
|
2016-05-19 20:44:22 +00:00 |
|
TargetInfo
|
|
|
|
BitTracker.cpp
|
|
|
|
BitTracker.h
|
|
|
|
CMakeLists.txt
|
Touch Hexagon/CMakeLists.txt to regenerate build files, since r268641 complains of missing HexagonAlias.td on ninja.
|
2016-05-05 19:28:01 +00:00 |
|
Hexagon.h
|
|
|
|
Hexagon.td
|
[Hexagon] Merge HexagonAlias.td into HexagonInstrAlias.td, NFC
|
2016-05-05 16:19:36 +00:00 |
|
HexagonAsmPrinter.cpp
|
|
|
|
HexagonAsmPrinter.h
|
|
|
|
HexagonBitSimplify.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonBitTracker.cpp
|
|
|
|
HexagonBitTracker.h
|
|
|
|
HexagonBlockRanges.cpp
|
[Hexagon] Properly close live range in HexagonBlockRanges
|
2016-04-22 17:27:22 +00:00 |
|
HexagonBlockRanges.h
|
|
|
|
HexagonBranchRelaxation.cpp
|
|
|
|
HexagonCallingConv.td
|
|
|
|
HexagonCFGOptimizer.cpp
|
[scan-build] fix warnings emitted on LLVM Hexagon code base
|
2016-05-05 22:00:44 +00:00 |
|
HexagonCommonGEP.cpp
|
[scan-build] fix dead store warnings emitted on LLVM Hexagon code base
|
2016-05-13 13:13:59 +00:00 |
|
HexagonCopyToCombine.cpp
|
|
|
|
HexagonEarlyIfConv.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonExpandCondsets.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonFixupHwLoops.cpp
|
[scan-build] fix dead store warnings emitted on LLVM Hexagon code base
|
2016-05-13 13:13:59 +00:00 |
|
HexagonFrameLowering.cpp
|
[Hexagon] Make getCallerSavedRegs specific to a register class
|
2016-05-16 18:02:28 +00:00 |
|
HexagonFrameLowering.h
|
[Hexagon] Register save/restore functions do not follow regular conventions
|
2016-04-25 17:49:44 +00:00 |
|
HexagonGenExtract.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonGenInsert.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonGenMux.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonGenPredicate.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonHardwareLoops.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonInstrAlias.td
|
[Hexagon] Treat all conditional branches as predicted (not-taken by default)
|
2016-05-09 18:22:07 +00:00 |
|
HexagonInstrEnc.td
|
|
|
|
HexagonInstrFormats.td
|
|
|
|
HexagonInstrFormatsV4.td
|
|
|
|
HexagonInstrFormatsV60.td
|
|
|
|
HexagonInstrInfo.cpp
|
[Hexagon] Simplify HexagonInstrInfo::isPredicable
|
2016-05-16 16:56:10 +00:00 |
|
HexagonInstrInfo.h
|
[Hexagon] Optimize addressing modes for load/store
|
2016-04-29 15:49:13 +00:00 |
|
HexagonInstrInfo.td
|
[Hexagon] Treat all conditional branches as predicted (not-taken by default)
|
2016-05-09 18:22:07 +00:00 |
|
HexagonInstrInfoV3.td
|
[Hexagon] Register save/restore functions do not follow regular conventions
|
2016-04-25 17:49:44 +00:00 |
|
HexagonInstrInfoV4.td
|
[Hexagon] Register save/restore functions do not follow regular conventions
|
2016-04-25 17:49:44 +00:00 |
|
HexagonInstrInfoV5.td
|
|
|
|
HexagonInstrInfoV60.td
|
|
|
|
HexagonInstrInfoVector.td
|
|
|
|
HexagonIntrinsics.td
|
[Hexagon] Handle operand type differences for A2_tfrpi
|
2016-05-05 15:29:47 +00:00 |
|
HexagonIntrinsicsDerived.td
|
|
|
|
HexagonIntrinsicsV3.td
|
|
|
|
HexagonIntrinsicsV4.td
|
[Hexagon] Use common Pat classes for selecting code for intrinsics
|
2016-04-22 18:05:55 +00:00 |
|
HexagonIntrinsicsV5.td
|
[Hexagon] Use common Pat classes for selecting code for intrinsics
|
2016-04-22 18:05:55 +00:00 |
|
HexagonIntrinsicsV60.td
|
[Hexagon] Use common Pat classes for selecting code for intrinsics
|
2016-04-22 18:05:55 +00:00 |
|
HexagonISelDAGToDAG.cpp
|
[Hexagon] Remove dead nodes from SelectionDAG to avoid cycles
|
2016-05-13 18:48:15 +00:00 |
|
HexagonISelLowering.cpp
|
[Hexagon] Recognize "q" and "v" in inline-asm as register constraints
|
2016-05-18 14:34:51 +00:00 |
|
HexagonISelLowering.h
|
[Hexagon] Recognize "q" and "v" in inline-asm as register constraints
|
2016-05-18 14:34:51 +00:00 |
|
HexagonIsetDx.td
|
|
|
|
HexagonMachineFunctionInfo.cpp
|
|
|
|
HexagonMachineFunctionInfo.h
|
|
|
|
HexagonMachineScheduler.cpp
|
|
|
|
HexagonMachineScheduler.h
|
|
|
|
HexagonMCInstLower.cpp
|
|
|
|
HexagonNewValueJump.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonOperands.td
|
|
|
|
HexagonOptAddrMode.cpp
|
[Hexagon] Move some debug-only variable declarations into DEBUG
|
2016-05-23 17:31:30 +00:00 |
|
HexagonOptimizeSZextends.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonPeephole.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonRDF.cpp
|
|
|
|
HexagonRDF.h
|
|
|
|
HexagonRDFOpt.cpp
|
[RDF] Add option to keep dead phi nodes in DFG
|
2016-04-28 20:17:06 +00:00 |
|
HexagonRegisterInfo.cpp
|
[Hexagon] Make getCallerSavedRegs specific to a register class
|
2016-05-16 18:02:28 +00:00 |
|
HexagonRegisterInfo.h
|
[Hexagon] Make getCallerSavedRegs specific to a register class
|
2016-05-16 18:02:28 +00:00 |
|
HexagonRegisterInfo.td
|
[Hexagon] Properly recognize register alt names
|
2016-04-21 19:49:53 +00:00 |
|
HexagonSchedule.td
|
|
|
|
HexagonScheduleV4.td
|
|
|
|
HexagonScheduleV55.td
|
|
|
|
HexagonScheduleV60.td
|
|
|
|
HexagonSelectCCInfo.td
|
|
|
|
HexagonSelectionDAGInfo.cpp
|
|
|
|
HexagonSelectionDAGInfo.h
|
|
|
|
HexagonSplitConst32AndConst64.cpp
|
[Hexagon] Expand handling of the small-data/bss section
|
2016-04-21 18:56:45 +00:00 |
|
HexagonSplitDouble.cpp
|
[MIB] Create a helper function getRegState to extract all register flags
|
2016-05-13 13:01:19 +00:00 |
|
HexagonStoreWidening.cpp
|
Add optimization bisect opt-in calls for Hexagon passes
|
2016-04-26 19:46:28 +00:00 |
|
HexagonSubtarget.cpp
|
|
|
|
HexagonSubtarget.h
|
|
|
|
HexagonSystemInst.td
|
[Hexagon] Add definitions for trap/pause instructions
|
2016-04-22 16:25:00 +00:00 |
|
HexagonTargetMachine.cpp
|
Delete Reloc::Default.
|
2016-05-18 22:04:49 +00:00 |
|
HexagonTargetMachine.h
|
Delete Reloc::Default.
|
2016-05-18 22:04:49 +00:00 |
|
HexagonTargetObjectFile.cpp
|
[Hexagon] Expand handling of the small-data/bss section
|
2016-04-21 18:56:45 +00:00 |
|
HexagonTargetObjectFile.h
|
[Hexagon] Expand handling of the small-data/bss section
|
2016-04-21 18:56:45 +00:00 |
|
HexagonTargetStreamer.h
|
|
|
|
HexagonTargetTransformInfo.cpp
|
|
|
|
HexagonTargetTransformInfo.h
|
|
|
|
HexagonVLIWPacketizer.cpp
|
[Hexagon] Be careful about anti-dependencies with a call in packetizer
|
2016-05-06 19:13:38 +00:00 |
|
HexagonVLIWPacketizer.h
|
|
|
|
LLVMBuild.txt
|
|
|
|
RDFCopy.cpp
|
[RDF] Handle undefined registers in RDF copy propagation
|
2016-04-28 15:09:19 +00:00 |
|
RDFCopy.h
|
|
|
|
RDFDeadCode.cpp
|
|
|
|
RDFDeadCode.h
|
|
|
|
RDFGraph.cpp
|
[scan-build] fix warnings emitted on LLVM Hexagon code base
|
2016-05-05 22:00:44 +00:00 |
|
RDFGraph.h
|
[RDF] Add option to keep dead phi nodes in DFG
|
2016-04-28 20:17:06 +00:00 |
|
RDFLiveness.cpp
|
[Hexagon] Optimize addressing modes for load/store
|
2016-04-29 15:49:13 +00:00 |
|
RDFLiveness.h
|
[Hexagon] Optimize addressing modes for load/store
|
2016-04-29 15:49:13 +00:00 |
