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ea7a0c0467
This makes it possible to distinguish between mesa shaders and other kernels even in the presence of compute shaders. Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Differential Revision: http://reviews.llvm.org/D18559 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265589 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
1.0 KiB
LLVM
25 lines
1.0 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=GCN %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN %s
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;GCN-LABEL: {{^}}mbcnt_intrinsics:
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;GCN: v_mbcnt_lo_u32_b32_e64 [[LO:v[0-9]+]], -1, 0
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;SI: v_mbcnt_hi_u32_b32_e32 {{v[0-9]+}}, -1, [[LO]]
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;VI: v_mbcnt_hi_u32_b32_e64 {{v[0-9]+}}, -1, [[LO]]
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define amdgpu_ps void @mbcnt_intrinsics(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) {
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main_body:
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1
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%hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) #1
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%4 = bitcast i32 %hi to float
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %4, float %4, float %4, float %4)
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ret void
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
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declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #1 = { nounwind readnone }
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