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ea7a0c0467
This makes it possible to distinguish between mesa shaders and other kernels even in the presence of compute shaders. Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Differential Revision: http://reviews.llvm.org/D18559 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265589 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
3.5 KiB
LLVM
82 lines
3.5 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
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;REQUIRES: asserts
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define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
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main_body:
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%0 = extractelement <4 x float> %reg1, i32 0
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%1 = extractelement <4 x float> %reg1, i32 1
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%2 = extractelement <4 x float> %reg1, i32 2
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%3 = extractelement <4 x float> %reg1, i32 3
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%4 = fcmp ult float %1, 0.000000e+00
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%5 = select i1 %4, float 1.000000e+00, float 0.000000e+00
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%6 = fsub float -0.000000e+00, %5
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%7 = fptosi float %6 to i32
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%8 = bitcast i32 %7 to float
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%9 = fcmp ult float %0, 5.700000e+01
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%10 = select i1 %9, float 1.000000e+00, float 0.000000e+00
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%11 = fsub float -0.000000e+00, %10
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%12 = fptosi float %11 to i32
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%13 = bitcast i32 %12 to float
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%14 = bitcast float %8 to i32
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%15 = bitcast float %13 to i32
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%16 = and i32 %14, %15
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%17 = bitcast i32 %16 to float
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%18 = bitcast float %17 to i32
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%19 = icmp ne i32 %18, 0
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%20 = fcmp ult float %0, 0.000000e+00
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%21 = select i1 %20, float 1.000000e+00, float 0.000000e+00
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%22 = fsub float -0.000000e+00, %21
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%23 = fptosi float %22 to i32
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%24 = bitcast i32 %23 to float
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%25 = bitcast float %24 to i32
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%26 = icmp ne i32 %25, 0
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br i1 %19, label %IF, label %ELSE
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IF: ; preds = %main_body
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%. = select i1 %26, float 0.000000e+00, float 1.000000e+00
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%.18 = select i1 %26, float 1.000000e+00, float 0.000000e+00
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br label %ENDIF
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ELSE: ; preds = %main_body
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br i1 %26, label %ENDIF, label %ELSE17
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ENDIF: ; preds = %ELSE17, %ELSE, %IF
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%temp1.0 = phi float [ %., %IF ], [ %48, %ELSE17 ], [ 0.000000e+00, %ELSE ]
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%temp2.0 = phi float [ 0.000000e+00, %IF ], [ %49, %ELSE17 ], [ 1.000000e+00, %ELSE ]
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%temp.0 = phi float [ %.18, %IF ], [ %47, %ELSE17 ], [ 0.000000e+00, %ELSE ]
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%27 = call float @llvm.AMDGPU.clamp.f32(float %temp.0, float 0.000000e+00, float 1.000000e+00)
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%28 = call float @llvm.AMDGPU.clamp.f32(float %temp1.0, float 0.000000e+00, float 1.000000e+00)
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%29 = call float @llvm.AMDGPU.clamp.f32(float %temp2.0, float 0.000000e+00, float 1.000000e+00)
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%30 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
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%31 = insertelement <4 x float> undef, float %27, i32 0
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%32 = insertelement <4 x float> %31, float %28, i32 1
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%33 = insertelement <4 x float> %32, float %29, i32 2
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%34 = insertelement <4 x float> %33, float %30, i32 3
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call void @llvm.R600.store.swizzle(<4 x float> %34, i32 0, i32 0)
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ret void
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ELSE17: ; preds = %ELSE
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%35 = fadd float 0.000000e+00, 0x3FC99999A0000000
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%36 = fadd float 0.000000e+00, 0x3FC99999A0000000
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%37 = fadd float 0.000000e+00, 0x3FC99999A0000000
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%38 = fadd float %35, 0x3FC99999A0000000
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%39 = fadd float %36, 0x3FC99999A0000000
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%40 = fadd float %37, 0x3FC99999A0000000
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%41 = fadd float %38, 0x3FC99999A0000000
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%42 = fadd float %39, 0x3FC99999A0000000
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%43 = fadd float %40, 0x3FC99999A0000000
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%44 = fadd float %41, 0x3FC99999A0000000
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%45 = fadd float %42, 0x3FC99999A0000000
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%46 = fadd float %43, 0x3FC99999A0000000
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%47 = fadd float %44, 0x3FC99999A0000000
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%48 = fadd float %45, 0x3FC99999A0000000
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%49 = fadd float %46, 0x3FC99999A0000000
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br label %ENDIF
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}
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declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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attributes #0 = { readnone }
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