mirror of
https://github.com/RPCSX/llvm.git
synced 2024-11-28 06:00:28 +00:00
acccef0ba4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297747 91177308-0d34-0410-b5e6-96231b3b80d8
575 lines
15 KiB
LLVM
575 lines
15 KiB
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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define i64 @rem_signed(i64 %x1, i64 %y2) {
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; CHECK-LABEL: @rem_signed(
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; CHECK-NEXT: [[R:%.*]] = srem i64 %x1, %y2
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; CHECK-NEXT: ret i64 [[R]]
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;
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%r = sdiv i64 %x1, %y2
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%r7 = mul i64 %r, %y2
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%r8 = sub i64 %x1, %r7
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ret i64 %r8
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}
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define <4 x i32> @rem_signed_vec(<4 x i32> %t, <4 x i32> %u) {
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; CHECK-LABEL: @rem_signed_vec(
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; CHECK-NEXT: [[K:%.*]] = srem <4 x i32> %t, %u
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; CHECK-NEXT: ret <4 x i32> [[K]]
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;
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%k = sdiv <4 x i32> %t, %u
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%l = mul <4 x i32> %k, %u
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%m = sub <4 x i32> %t, %l
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ret <4 x i32> %m
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}
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define i64 @rem_unsigned(i64 %x1, i64 %y2) {
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; CHECK-LABEL: @rem_unsigned(
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; CHECK-NEXT: [[R:%.*]] = urem i64 %x1, %y2
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; CHECK-NEXT: ret i64 [[R]]
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;
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%r = udiv i64 %x1, %y2
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%r7 = mul i64 %r, %y2
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%r8 = sub i64 %x1, %r7
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ret i64 %r8
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}
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; PR28672 - https://llvm.org/bugs/show_bug.cgi?id=28672
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define i8 @big_divisor(i8 %x) {
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; CHECK-LABEL: @big_divisor(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 %x, -127
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; CHECK-NEXT: [[TMP2:%.*]] = add i8 %x, 127
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; CHECK-NEXT: [[REM:%.*]] = select i1 [[TMP1]], i8 %x, i8 [[TMP2]]
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; CHECK-NEXT: ret i8 [[REM]]
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;
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%rem = urem i8 %x, 129
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ret i8 %rem
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}
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define i5 @biggest_divisor(i5 %x) {
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; CHECK-LABEL: @biggest_divisor(
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; CHECK-NEXT: [[NOT_:%.*]] = icmp eq i5 %x, -1
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; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[NOT_]] to i5
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; CHECK-NEXT: [[REM:%.*]] = add i5 [[TMP1]], %x
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; CHECK-NEXT: ret i5 [[REM]]
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;
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%rem = urem i5 %x, -1
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ret i5 %rem
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}
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; TODO: Should vector subtract of constant be canonicalized to add?
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define <2 x i4> @big_divisor_vec(<2 x i4> %x) {
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; CHECK-LABEL: @big_divisor_vec(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i4> %x, <i4 -3, i4 -3>
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; CHECK-NEXT: [[TMP2:%.*]] = sub <2 x i4> %x, <i4 -3, i4 -3>
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; CHECK-NEXT: [[REM:%.*]] = select <2 x i1> [[TMP1]], <2 x i4> %x, <2 x i4> [[TMP2]]
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; CHECK-NEXT: ret <2 x i4> [[REM]]
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;
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%rem = urem <2 x i4> %x, <i4 13, i4 13>
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ret <2 x i4> %rem
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}
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define i8 @urem1(i8 %x, i8 %y) {
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; CHECK-LABEL: @urem1(
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; CHECK-NEXT: [[A:%.*]] = urem i8 %x, %y
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; CHECK-NEXT: ret i8 [[A]]
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;
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%A = udiv i8 %x, %y
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%B = mul i8 %A, %y
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%C = sub i8 %x, %B
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ret i8 %C
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}
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define i8 @srem1(i8 %x, i8 %y) {
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; CHECK-LABEL: @srem1(
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; CHECK-NEXT: [[A:%.*]] = srem i8 %x, %y
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; CHECK-NEXT: ret i8 [[A]]
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;
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%A = sdiv i8 %x, %y
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%B = mul i8 %A, %y
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%C = sub i8 %x, %B
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ret i8 %C
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}
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define i8 @urem2(i8 %x, i8 %y) {
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; CHECK-LABEL: @urem2(
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; CHECK-NEXT: [[A:%.*]] = urem i8 %x, %y
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; CHECK-NEXT: [[C:%.*]] = sub i8 0, [[A]]
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; CHECK-NEXT: ret i8 [[C]]
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;
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%A = udiv i8 %x, %y
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%B = mul i8 %A, %y
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%C = sub i8 %B, %x
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ret i8 %C
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}
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define i8 @urem3(i8 %x) {
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; CHECK-LABEL: @urem3(
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; CHECK-NEXT: [[A:%.*]] = urem i8 %x, 3
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; CHECK-NEXT: [[B1:%.*]] = sub i8 %x, [[A]]
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; CHECK-NEXT: [[C:%.*]] = add i8 [[B1]], %x
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; CHECK-NEXT: ret i8 [[C]]
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;
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%A = udiv i8 %x, 3
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%B = mul i8 %A, -3
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%C = sub i8 %x, %B
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ret i8 %C
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}
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; (((X / Y) * Y) / Y) -> X / Y
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define i32 @sdiv_mul_sdiv(i32 %x, i32 %y) {
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; CHECK-LABEL: @sdiv_mul_sdiv(
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; CHECK-NEXT: [[R:%.*]] = sdiv i32 %x, %y
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; CHECK-NEXT: ret i32 [[R]]
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;
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%div = sdiv i32 %x, %y
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%mul = mul i32 %div, %y
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%r = sdiv i32 %mul, %y
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ret i32 %r
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}
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; (((X / Y) * Y) / Y) -> X / Y
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define i32 @udiv_mul_udiv(i32 %x, i32 %y) {
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; CHECK-LABEL: @udiv_mul_udiv(
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; CHECK-NEXT: [[R:%.*]] = udiv i32 %x, %y
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; CHECK-NEXT: ret i32 [[R]]
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;
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%div = udiv i32 %x, %y
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%mul = mul i32 %div, %y
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%r = udiv i32 %mul, %y
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ret i32 %r
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}
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define i32 @test1(i32 %A) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: ret i32 0
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;
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%B = srem i32 %A, 1 ; ISA constant 0
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ret i32 %B
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}
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define i32 @test2(i32 %A) { ; 0 % X = 0, we don't need to preserve traps
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: ret i32 0
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;
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%B = srem i32 0, %A
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ret i32 %B
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}
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define i32 @test3(i32 %A) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: [[B:%.*]] = and i32 %A, 7
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; CHECK-NEXT: ret i32 [[B]]
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;
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%B = urem i32 %A, 8
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ret i32 %B
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}
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define <2 x i32> @vec_power_of_2_constant_splat_divisor(<2 x i32> %A) {
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; CHECK-LABEL: @vec_power_of_2_constant_splat_divisor(
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; CHECK-NEXT: [[B:%.*]] = and <2 x i32> %A, <i32 7, i32 7>
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; CHECK-NEXT: ret <2 x i32> [[B]]
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;
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%B = urem <2 x i32> %A, <i32 8, i32 8>
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ret <2 x i32> %B
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}
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define <2 x i19> @weird_vec_power_of_2_constant_splat_divisor(<2 x i19> %A) {
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; CHECK-LABEL: @weird_vec_power_of_2_constant_splat_divisor(
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; CHECK-NEXT: [[B:%.*]] = and <2 x i19> %A, <i19 7, i19 7>
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; CHECK-NEXT: ret <2 x i19> [[B]]
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;
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%B = urem <2 x i19> %A, <i19 8, i19 8>
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ret <2 x i19> %B
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}
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define i1 @test3a(i32 %A) {
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; CHECK-LABEL: @test3a(
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; CHECK-NEXT: [[B1:%.*]] = and i32 %A, 7
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; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[B1]], 0
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; CHECK-NEXT: ret i1 [[C]]
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;
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%B = srem i32 %A, -8
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%C = icmp ne i32 %B, 0
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ret i1 %C
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}
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define <2 x i1> @test3a_vec(<2 x i32> %A) {
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; CHECK-LABEL: @test3a_vec(
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; CHECK-NEXT: [[B1:%.*]] = and <2 x i32> %A, <i32 7, i32 7>
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; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i32> [[B1]], zeroinitializer
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; CHECK-NEXT: ret <2 x i1> [[C]]
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;
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%B = srem <2 x i32> %A, <i32 -8, i32 -8>
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%C = icmp ne <2 x i32> %B, zeroinitializer
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ret <2 x i1> %C
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}
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define i32 @test4(i32 %X, i1 %C) {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: [[TMP1:%.*]] = select i1 %C, i32 0, i32 7
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; CHECK-NEXT: [[R:%.*]] = and i32 [[TMP1]], %X
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; CHECK-NEXT: ret i32 [[R]]
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;
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%V = select i1 %C, i32 1, i32 8
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%R = urem i32 %X, %V
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ret i32 %R
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}
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define i32 @test5(i32 %X, i8 %B) {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: [[SHIFT_UPGRD_1:%.*]] = zext i8 %B to i32
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; CHECK-NEXT: [[AMT:%.*]] = shl nuw i32 32, [[SHIFT_UPGRD_1]]
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[AMT]], -1
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; CHECK-NEXT: [[V:%.*]] = and i32 [[TMP1]], %X
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; CHECK-NEXT: ret i32 [[V]]
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;
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%shift.upgrd.1 = zext i8 %B to i32
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%Amt = shl i32 32, %shift.upgrd.1
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%V = urem i32 %X, %Amt
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ret i32 %V
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}
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define i32 @test6(i32 %A) {
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: ret i32 undef
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;
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%B = srem i32 %A, 0 ;; undef
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ret i32 %B
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}
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define i32 @test7(i32 %A) {
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: ret i32 0
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;
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%B = mul i32 %A, 8
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%C = srem i32 %B, 4
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ret i32 %C
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}
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define i32 @test8(i32 %A) {
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; CHECK-LABEL: @test8(
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; CHECK-NEXT: ret i32 0
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;
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%B = shl i32 %A, 4
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%C = srem i32 %B, 8
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ret i32 %C
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}
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define i32 @test9(i32 %A) {
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; CHECK-LABEL: @test9(
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; CHECK-NEXT: ret i32 0
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;
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%B = mul i32 %A, 64
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%C = urem i32 %B, 32
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ret i32 %C
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}
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define i32 @test10(i8 %c) {
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; CHECK-LABEL: @test10(
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; CHECK-NEXT: ret i32 0
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;
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%tmp.1 = zext i8 %c to i32
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%tmp.2 = mul i32 %tmp.1, 4
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%tmp.3 = sext i32 %tmp.2 to i64
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%tmp.5 = urem i64 %tmp.3, 4
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%tmp.6 = trunc i64 %tmp.5 to i32
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ret i32 %tmp.6
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}
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define i32 @test11(i32 %i) {
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; CHECK-LABEL: @test11(
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; CHECK-NEXT: ret i32 0
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;
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%tmp.1 = and i32 %i, -2
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%tmp.3 = mul i32 %tmp.1, 2
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%tmp.5 = urem i32 %tmp.3, 4
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ret i32 %tmp.5
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}
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define i32 @test12(i32 %i) {
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; CHECK-LABEL: @test12(
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; CHECK-NEXT: ret i32 0
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;
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%tmp.1 = and i32 %i, -4
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%tmp.5 = srem i32 %tmp.1, 2
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ret i32 %tmp.5
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}
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define i32 @test13(i32 %i) {
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; CHECK-LABEL: @test13(
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; CHECK-NEXT: ret i32 0
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;
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%x = srem i32 %i, %i
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ret i32 %x
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}
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define i64 @test14(i64 %x, i32 %y) {
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; CHECK-LABEL: @test14(
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %y
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[ZEXT]], -1
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; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP1]], %x
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; CHECK-NEXT: ret i64 [[UREM]]
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;
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%shl = shl i32 1, %y
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%zext = zext i32 %shl to i64
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%urem = urem i64 %x, %zext
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ret i64 %urem
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}
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define i64 @test15(i32 %x, i32 %y) {
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; CHECK-LABEL: @test15(
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; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, %y
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[SHL]], -1
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], %x
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; CHECK-NEXT: [[UREM:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: ret i64 [[UREM]]
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;
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%shl = shl i32 1, %y
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%zext0 = zext i32 %shl to i64
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%zext1 = zext i32 %x to i64
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%urem = urem i64 %zext1, %zext0
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ret i64 %urem
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}
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define i32 @test16(i32 %x, i32 %y) {
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; CHECK-LABEL: @test16(
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 %y, 11
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], 4
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; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], 3
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[TMP1]], %x
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; CHECK-NEXT: ret i32 [[REM]]
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;
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%shr = lshr i32 %y, 11
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%and = and i32 %shr, 4
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%add = add i32 %and, 4
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%rem = urem i32 %x, %add
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ret i32 %rem
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}
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define i32 @test17(i32 %X) {
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; CHECK-LABEL: @test17(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 %X, 1
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; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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%A = urem i32 1, %X
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ret i32 %A
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}
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define i32 @test18(i16 %x, i32 %y) {
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; CHECK-LABEL: @test18(
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; CHECK-NEXT: [[TMP1:%.*]] = shl i16 %x, 3
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; CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 32
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; CHECK-NEXT: [[TMP3:%.*]] = xor i16 [[TMP2]], 63
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; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], %y
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; CHECK-NEXT: ret i32 [[TMP5]]
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;
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%1 = and i16 %x, 4
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%2 = icmp ne i16 %1, 0
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%3 = select i1 %2, i32 32, i32 64
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%4 = urem i32 %y, %3
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ret i32 %4
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}
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define i32 @test19(i32 %x, i32 %y) {
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; CHECK-LABEL: @test19(
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; CHECK-NEXT: [[A:%.*]] = shl i32 1, %x
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; CHECK-NEXT: [[B:%.*]] = shl i32 1, %y
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; CHECK-NEXT: [[C:%.*]] = and i32 [[A]], [[B]]
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; CHECK-NEXT: [[D:%.*]] = add i32 [[C]], [[A]]
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[D]], -1
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; CHECK-NEXT: [[E:%.*]] = and i32 [[TMP1]], %y
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; CHECK-NEXT: ret i32 [[E]]
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;
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%A = shl i32 1, %x
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%B = shl i32 1, %y
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%C = and i32 %A, %B
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%D = add i32 %C, %A
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%E = urem i32 %y, %D
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ret i32 %E
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}
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define <2 x i64> @test20(<2 x i64> %X, <2 x i1> %C) {
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; CHECK-LABEL: @test20(
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; CHECK-NEXT: [[R:%.*]] = select <2 x i1> %C, <2 x i64> <i64 1, i64 2>, <2 x i64> zeroinitializer
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; CHECK-NEXT: ret <2 x i64> [[R]]
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;
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%V = select <2 x i1> %C, <2 x i64> <i64 1, i64 2>, <2 x i64> <i64 8, i64 9>
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%R = urem <2 x i64> %V, <i64 2, i64 3>
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ret <2 x i64> %R
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}
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define i32 @test21(i1 %c0, i32* %p) {
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; CHECK-LABEL: @test21(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 %c0, label %if.then, label %if.end
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; CHECK: if.then:
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; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* %p, align 4
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; CHECK-NEXT: [[PHITMP:%.*]] = srem i32 [[V]], 5
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; CHECK-NEXT: br label %if.end
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; CHECK: if.end:
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; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[PHITMP]], %if.then ], [ 0, %entry ]
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; CHECK-NEXT: ret i32 [[LHS]]
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;
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entry:
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br i1 %c0, label %if.then, label %if.end
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if.then:
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%v = load volatile i32, i32* %p
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br label %if.end
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if.end:
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%lhs = phi i32 [ %v, %if.then ], [ 5, %entry ]
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%rem = srem i32 %lhs, 5
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ret i32 %rem
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}
|
|
|
|
@a = common global [5 x i16] zeroinitializer, align 2
|
|
@b = common global i16 0, align 2
|
|
|
|
define i32 @pr27968_0(i1 %c0, i32* %p) {
|
|
; CHECK-LABEL: @pr27968_0(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: br i1 %c0, label %if.then, label %if.end
|
|
; CHECK: if.then:
|
|
; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* %p, align 4
|
|
; CHECK-NEXT: br label %if.end
|
|
; CHECK: if.end:
|
|
; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[V]], %if.then ], [ 5, %entry ]
|
|
; CHECK-NEXT: br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label [[REM]].is.safe, label [[REM]].is.unsafe
|
|
; CHECK: rem.is.safe:
|
|
; CHECK-NEXT: [[REM:%.*]] = srem i32 [[LHS]], zext (i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b) to i32)
|
|
; CHECK-NEXT: ret i32 [[REM]]
|
|
; CHECK: rem.is.unsafe:
|
|
; CHECK-NEXT: ret i32 0
|
|
;
|
|
entry:
|
|
br i1 %c0, label %if.then, label %if.end
|
|
|
|
if.then:
|
|
%v = load volatile i32, i32* %p
|
|
br label %if.end
|
|
|
|
if.end:
|
|
%lhs = phi i32 [ %v, %if.then ], [ 5, %entry ]
|
|
br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label %rem.is.safe, label %rem.is.unsafe
|
|
|
|
rem.is.safe:
|
|
%rem = srem i32 %lhs, zext (i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b) to i32)
|
|
ret i32 %rem
|
|
|
|
rem.is.unsafe:
|
|
ret i32 0
|
|
}
|
|
|
|
define i32 @pr27968_1(i1 %c0, i1 %always_false, i32* %p) {
|
|
; CHECK-LABEL: @pr27968_1(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: br i1 %c0, label %if.then, label %if.end
|
|
; CHECK: if.then:
|
|
; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* %p, align 4
|
|
; CHECK-NEXT: br label %if.end
|
|
; CHECK: if.end:
|
|
; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[V]], %if.then ], [ 5, %entry ]
|
|
; CHECK-NEXT: br i1 %always_false, label [[REM]].is.safe, label [[REM]].is.unsafe
|
|
; CHECK: rem.is.safe:
|
|
; CHECK-NEXT: [[REM:%.*]] = srem i32 [[LHS]], -2147483648
|
|
; CHECK-NEXT: ret i32 [[REM]]
|
|
; CHECK: rem.is.unsafe:
|
|
; CHECK-NEXT: ret i32 0
|
|
;
|
|
entry:
|
|
br i1 %c0, label %if.then, label %if.end
|
|
|
|
if.then:
|
|
%v = load volatile i32, i32* %p
|
|
br label %if.end
|
|
|
|
if.end:
|
|
%lhs = phi i32 [ %v, %if.then ], [ 5, %entry ]
|
|
br i1 %always_false, label %rem.is.safe, label %rem.is.unsafe
|
|
|
|
rem.is.safe:
|
|
%rem = srem i32 %lhs, -2147483648
|
|
ret i32 %rem
|
|
|
|
rem.is.unsafe:
|
|
ret i32 0
|
|
}
|
|
|
|
define i32 @pr27968_2(i1 %c0, i32* %p) {
|
|
; CHECK-LABEL: @pr27968_2(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: br i1 %c0, label %if.then, label %if.end
|
|
; CHECK: if.then:
|
|
; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* %p, align 4
|
|
; CHECK-NEXT: br label %if.end
|
|
; CHECK: if.end:
|
|
; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[V]], %if.then ], [ 5, %entry ]
|
|
; CHECK-NEXT: br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label [[REM]].is.safe, label [[REM]].is.unsafe
|
|
; CHECK: rem.is.safe:
|
|
; CHECK-NEXT: [[REM:%.*]] = urem i32 [[LHS]], zext (i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b) to i32)
|
|
; CHECK-NEXT: ret i32 [[REM]]
|
|
; CHECK: rem.is.unsafe:
|
|
; CHECK-NEXT: ret i32 0
|
|
;
|
|
entry:
|
|
br i1 %c0, label %if.then, label %if.end
|
|
|
|
if.then:
|
|
%v = load volatile i32, i32* %p
|
|
br label %if.end
|
|
|
|
if.end:
|
|
%lhs = phi i32 [ %v, %if.then ], [ 5, %entry ]
|
|
br i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b), label %rem.is.safe, label %rem.is.unsafe
|
|
|
|
rem.is.safe:
|
|
%rem = urem i32 %lhs, zext (i1 icmp eq (i16* getelementptr inbounds ([5 x i16], [5 x i16]* @a, i64 0, i64 4), i16* @b) to i32)
|
|
ret i32 %rem
|
|
|
|
rem.is.unsafe:
|
|
ret i32 0
|
|
}
|
|
|
|
define i32 @pr27968_3(i1 %c0, i1 %always_false, i32* %p) {
|
|
; CHECK-LABEL: @pr27968_3(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: br i1 %c0, label %if.then, label %if.end
|
|
; CHECK: if.then:
|
|
; CHECK-NEXT: [[V:%.*]] = load volatile i32, i32* %p, align 4
|
|
; CHECK-NEXT: [[PHITMP:%.*]] = and i32 [[V]], 2147483647
|
|
; CHECK-NEXT: br label %if.end
|
|
; CHECK: if.end:
|
|
; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[PHITMP]], %if.then ], [ 5, %entry ]
|
|
; CHECK-NEXT: br i1 %always_false, label %rem.is.safe, label %rem.is.unsafe
|
|
; CHECK: rem.is.safe:
|
|
; CHECK-NEXT: ret i32 [[LHS]]
|
|
; CHECK: rem.is.unsafe:
|
|
; CHECK-NEXT: ret i32 0
|
|
;
|
|
entry:
|
|
br i1 %c0, label %if.then, label %if.end
|
|
|
|
if.then:
|
|
%v = load volatile i32, i32* %p
|
|
br label %if.end
|
|
|
|
if.end:
|
|
%lhs = phi i32 [ %v, %if.then ], [ 5, %entry ]
|
|
br i1 %always_false, label %rem.is.safe, label %rem.is.unsafe
|
|
|
|
rem.is.safe:
|
|
%rem = urem i32 %lhs, -2147483648
|
|
ret i32 %rem
|
|
|
|
rem.is.unsafe:
|
|
ret i32 0
|
|
}
|
|
|