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dccf5a1320
This was suggested as a DAG simplification in the review for rL297026 : http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170306/435253.html ...but let's start with IR since we have actual docs for IR (LangRef). Differential Revision: https://reviews.llvm.org/D30665 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297390 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
725 B
LLVM
22 lines
725 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define <4 x i32> @test_v4i32_splatconst_pow2(<4 x i32> %a0) {
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; CHECK-LABEL: @test_v4i32_splatconst_pow2(
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; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> %a0, <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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;
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%1 = urem <4 x i32> %a0, <i32 2, i32 2, i32 2, i32 2>
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ret <4 x i32> %1
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}
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define <4 x i32> @test_v4i32_const_pow2(<4 x i32> %a0) {
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; CHECK-LABEL: @test_v4i32_const_pow2(
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; CHECK-NEXT: [[TMP1:%.*]] = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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;
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%1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
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ret <4 x i32> %1
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}
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