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286599a8f9
Add GlobalISel skeleton, up to the point where we can select a ret void. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286573 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
993 B
C++
28 lines
993 B
C++
//===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the RegisterBankInfo class for ARM.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "ARMRegisterBankInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "You shouldn't build this"
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#endif
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ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
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: RegisterBankInfo(nullptr, 0) {}
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