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https://github.com/RPCSX/llvm.git
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a80d09e041
We don't need to copy the sret argument into %rax upon return. rdar://25671494 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267579 91177308-0d34-0410-b5e6-96231b3b80d8
207 lines
6.3 KiB
LLVM
207 lines
6.3 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown -O0 | FileCheck --check-prefix=CHECK-O0 %s
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@var = global i32 0
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; Test how llvm handles return type of {i16, i8}. The return value will be
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; passed in %eax and %dl.
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; CHECK-LABEL: test:
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; CHECK: movl %edi
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; CHECK: callq gen
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; CHECK: movsbl %dl
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; CHECK: addl %{{.*}}, %eax
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; CHECK-O0-LABEL: test
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; CHECK-O0: movl %edi
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; CHECK-O0: callq gen
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; CHECK-O0: movswl %ax
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; CHECK-O0: movsbl %dl
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; CHECK-O0: addl
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; CHECK-O0: movw %{{.*}}, %ax
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define i16 @test(i32 %key) {
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entry:
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%key.addr = alloca i32, align 4
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store i32 %key, i32* %key.addr, align 4
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%0 = load i32, i32* %key.addr, align 4
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%call = call swiftcc { i16, i8 } @gen(i32 %0)
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%v3 = extractvalue { i16, i8 } %call, 0
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%v1 = sext i16 %v3 to i32
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%v5 = extractvalue { i16, i8 } %call, 1
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%v2 = sext i8 %v5 to i32
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%add = add nsw i32 %v1, %v2
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%conv = trunc i32 %add to i16
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ret i16 %conv
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}
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declare swiftcc { i16, i8 } @gen(i32)
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; If we can't pass every return value in register, we will pass everything
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; in memroy. The caller provides space for the return value and passes
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; the address in %rax. The first input argument will be in %rdi.
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; CHECK-LABEL: test2:
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; CHECK: leaq (%rsp), %rax
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; CHECK: callq gen2
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; CHECK: movl (%rsp)
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; CHECK-DAG: addl 4(%rsp)
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; CHECK-DAG: addl 8(%rsp)
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; CHECK-DAG: addl 12(%rsp)
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; CHECK-DAG: addl 16(%rsp)
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; CHECK-O0-LABEL: test2:
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; CHECK-O0-DAG: leaq (%rsp), %rax
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; CHECK-O0: callq gen2
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; CHECK-O0-DAG: movl (%rsp)
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; CHECK-O0-DAG: movl 4(%rsp)
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; CHECK-O0-DAG: movl 8(%rsp)
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; CHECK-O0-DAG: movl 12(%rsp)
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; CHECK-O0-DAG: movl 16(%rsp)
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; CHECK-O0: addl
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; CHECK-O0: addl
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; CHECK-O0: addl
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; CHECK-O0: addl
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; CHECK-O0: movl %{{.*}}, %eax
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define i32 @test2(i32 %key) #0 {
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entry:
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%key.addr = alloca i32, align 4
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store i32 %key, i32* %key.addr, align 4
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%0 = load i32, i32* %key.addr, align 4
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%call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0)
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%v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 0
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%v5 = extractvalue { i32, i32, i32, i32, i32 } %call, 1
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%v6 = extractvalue { i32, i32, i32, i32, i32 } %call, 2
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%v7 = extractvalue { i32, i32, i32, i32, i32 } %call, 3
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%v8 = extractvalue { i32, i32, i32, i32, i32 } %call, 4
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%add = add nsw i32 %v3, %v5
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%add1 = add nsw i32 %add, %v6
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%add2 = add nsw i32 %add1, %v7
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%add3 = add nsw i32 %add2, %v8
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ret i32 %add3
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}
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; The address of the return value is passed in %rax.
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; On return, we don't keep the address in %rax.
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; CHECK-LABEL: gen2:
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; CHECK: movl %edi, 16(%rax)
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; CHECK: movl %edi, 12(%rax)
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; CHECK: movl %edi, 8(%rax)
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; CHECK: movl %edi, 4(%rax)
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; CHECK: movl %edi, (%rax)
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; CHECK-O0-LABEL: gen2:
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; CHECK-O0-DAG: movl %edi, 16(%rax)
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; CHECK-O0-DAG: movl %edi, 12(%rax)
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; CHECK-O0-DAG: movl %edi, 8(%rax)
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; CHECK-O0-DAG: movl %edi, 4(%rax)
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; CHECK-O0-DAG: movl %edi, (%rax)
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define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) {
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%Y = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %key, 0
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%Z = insertvalue { i32, i32, i32, i32, i32 } %Y, i32 %key, 1
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%Z2 = insertvalue { i32, i32, i32, i32, i32 } %Z, i32 %key, 2
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%Z3 = insertvalue { i32, i32, i32, i32, i32 } %Z2, i32 %key, 3
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%Z4 = insertvalue { i32, i32, i32, i32, i32 } %Z3, i32 %key, 4
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ret { i32, i32, i32, i32, i32 } %Z4
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}
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; The return value {i32, i32, i32, i32} will be returned via registers %eax,
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; %edx, %ecx, %r8d.
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; CHECK-LABEL: test3:
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; CHECK: callq gen3
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; CHECK: addl %edx, %eax
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; CHECK: addl %ecx, %eax
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; CHECK: addl %r8d, %eax
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; CHECK-O0-LABEL: test3:
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; CHECK-O0: callq gen3
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; CHECK-O0: addl %edx, %eax
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; CHECK-O0: addl %ecx, %eax
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; CHECK-O0: addl %r8d, %eax
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define i32 @test3(i32 %key) #0 {
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entry:
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%key.addr = alloca i32, align 4
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store i32 %key, i32* %key.addr, align 4
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%0 = load i32, i32* %key.addr, align 4
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%call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0)
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%v3 = extractvalue { i32, i32, i32, i32 } %call, 0
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%v5 = extractvalue { i32, i32, i32, i32 } %call, 1
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%v6 = extractvalue { i32, i32, i32, i32 } %call, 2
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%v7 = extractvalue { i32, i32, i32, i32 } %call, 3
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%add = add nsw i32 %v3, %v5
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%add1 = add nsw i32 %add, %v6
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%add2 = add nsw i32 %add1, %v7
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ret i32 %add2
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}
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declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key)
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; The return value {float, float, float, float} will be returned via registers
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; %xmm0, %xmm1, %xmm2, %xmm3.
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; CHECK-LABEL: test4:
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; CHECK: callq gen4
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; CHECK: addss %xmm1, %xmm0
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; CHECK: addss %xmm2, %xmm0
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; CHECK: addss %xmm3, %xmm0
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; CHECK-O0-LABEL: test4:
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; CHECK-O0: callq gen4
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; CHECK-O0: addss %xmm1, %xmm0
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; CHECK-O0: addss %xmm2, %xmm0
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; CHECK-O0: addss %xmm3, %xmm0
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define float @test4(float %key) #0 {
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entry:
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%key.addr = alloca float, align 4
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store float %key, float* %key.addr, align 4
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%0 = load float, float* %key.addr, align 4
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%call = call swiftcc { float, float, float, float } @gen4(float %0)
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%v3 = extractvalue { float, float, float, float } %call, 0
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%v5 = extractvalue { float, float, float, float } %call, 1
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%v6 = extractvalue { float, float, float, float } %call, 2
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%v7 = extractvalue { float, float, float, float } %call, 3
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%add = fadd float %v3, %v5
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%add1 = fadd float %add, %v6
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%add2 = fadd float %add1, %v7
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ret float %add2
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}
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declare swiftcc { float, float, float, float } @gen4(float %key)
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; CHECK-LABEL: consume_i1_ret:
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; CHECK: callq produce_i1_ret
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; CHECK: andb $1, %al
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; CHECK: andb $1, %dl
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; CHECK: andb $1, %cl
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; CHECK: andb $1, %r8b
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; CHECK-O0-LABEL: consume_i1_ret:
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; CHECK-O0: callq produce_i1_ret
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; CHECK-O0: andb $1, %al
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; CHECK-O0: andb $1, %dl
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; CHECK-O0: andb $1, %cl
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; CHECK-O0: andb $1, %r8b
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define void @consume_i1_ret() {
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%call = call swiftcc { i1, i1, i1, i1 } @produce_i1_ret()
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%v3 = extractvalue { i1, i1, i1, i1 } %call, 0
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%v5 = extractvalue { i1, i1, i1, i1 } %call, 1
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%v6 = extractvalue { i1, i1, i1, i1 } %call, 2
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%v7 = extractvalue { i1, i1, i1, i1 } %call, 3
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%val = zext i1 %v3 to i32
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store i32 %val, i32* @var
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%val2 = zext i1 %v5 to i32
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store i32 %val2, i32* @var
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%val3 = zext i1 %v6 to i32
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store i32 %val3, i32* @var
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%val4 = zext i1 %v7 to i32
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store i32 %val4, i32* @var
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ret void
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}
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declare swiftcc { i1, i1, i1, i1 } @produce_i1_ret()
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; CHECK-LABEL: foo:
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; CHECK: movq %rdi, (%rax)
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; CHECK-O0-LABEL: foo:
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; CHECK-O0: movq %rdi, (%rax)
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define swiftcc void @foo(i64* sret %agg.result, i64 %val) {
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store i64 %val, i64* %agg.result
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ret void
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}
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