llvm/lib/Target/Sparc
Filipe Cabecinhas 2fd54348ae Unify XDEBUG and EXPENSIVE_CHECKS (into the latter), and add an option to the cmake build to enable them.
Summary:
Historically, we had a switch in the Makefiles for turning on "expensive
checks". This has never been ported to the cmake build, but the
(dead-ish) code is still around.

This will also make it easier to turn it on in buildbots.

Reviewers: chandlerc

Subscribers: jyknight, mzolotukhin, RKSimon, gberry, llvm-commits

Differential Revision: http://reviews.llvm.org/D19723

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268050 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 15:22:48 +00:00
..
AsmParser Sparc: silently ignore .proc assembler directive 2016-03-28 14:00:11 +00:00
Disassembler This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
InstPrinter This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
MCTargetDesc Remove autoconf support 2016-01-26 21:29:08 +00:00
TargetInfo Remove autoconf support 2016-01-26 21:29:08 +00:00
CMakeLists.txt Remove getDataLayout() from TargetSelectionDAGInfo (had no users) 2015-07-09 02:10:08 +00:00
DelaySlotFiller.cpp The following code would not work before this patch, due to the inability to take the address of a global object: 2016-04-22 08:13:47 +00:00
LLVMBuild.txt
README.txt Initial test commit only 2016-02-26 11:38:24 +00:00
Sparc.h This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
Sparc.td [Sparc] This provides support for itineraries on Sparc. 2016-04-22 08:17:17 +00:00
SparcAsmPrinter.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
SparcCallingConv.td [Sparc] Implement i64 load/store support for 32-bit sparc. 2015-08-10 19:11:39 +00:00
SparcFrameLowering.cpp Unify XDEBUG and EXPENSIVE_CHECKS (into the latter), and add an option to the cmake build to enable them. 2016-04-29 15:22:48 +00:00
SparcFrameLowering.h Change eliminateCallFramePseudoInstr() to return an iterator 2016-03-31 18:33:38 +00:00
SparcInstr64Bit.td [SPARC] Use AtomicExpandPass to expand AtomicRMW instructions. 2016-03-29 19:09:54 +00:00
SparcInstrAliases.td This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
SparcInstrFormats.td [Sparc] This provides support for itineraries on Sparc. 2016-04-22 08:17:17 +00:00
SparcInstrInfo.cpp [Sparc] Fix build error introduced by rL267545. 2016-04-26 10:43:47 +00:00
SparcInstrInfo.h [SPARC] [SSP] Add support for LOAD_STACK_GUARD. 2016-04-26 10:37:14 +00:00
SparcInstrInfo.td [Sparc] This provides support for itineraries on Sparc. 2016-04-22 08:17:17 +00:00
SparcInstrVIS.td
SparcISelDAGToDAG.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
SparcISelLowering.cpp [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in TargetLoweringBase. This is what the majority of the targets want and removes a bunch of code. Set it to Legal explicitly in the few cases where that's the desired behavior. 2016-04-28 03:34:31 +00:00
SparcISelLowering.h [SPARC] [SSP] Add support for LOAD_STACK_GUARD. 2016-04-26 10:37:14 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
SparcMCInstLower.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
SparcRegisterInfo.cpp [Sparc] Support user-specified stack object overalignment. 2015-08-21 04:17:56 +00:00
SparcRegisterInfo.h [Sparc] Support user-specified stack object overalignment. 2015-08-21 04:17:56 +00:00
SparcRegisterInfo.td The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. 2016-02-27 12:49:59 +00:00
SparcSchedule.td [Sparc] This provides support for itineraries on Sparc. 2016-04-22 08:17:17 +00:00
SparcSubtarget.cpp [SPARC] [SSP] Add support for LOAD_STACK_GUARD. 2016-04-26 10:37:14 +00:00
SparcSubtarget.h [SPARC] [SSP] Add support for LOAD_STACK_GUARD. 2016-04-26 10:37:14 +00:00
SparcTargetMachine.cpp Replace string GNU Triples with llvm::Triple in TargetMachine. NFC. 2015-06-11 19:41:26 +00:00
SparcTargetMachine.h Replace string GNU Triples with llvm::Triple in TargetMachine. NFC. 2015-06-11 19:41:26 +00:00
SparcTargetObjectFile.cpp MC: Clean up MCExpr naming. NFC. 2015-05-30 01:25:56 +00:00
SparcTargetObjectFile.h
SparcTargetStreamer.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.