llvm/test/CodeGen/PowerPC/2012-10-11-dynalloc.ll
Ulrich Weigand b64e2115de Do not consider a machine instruction that uses and defines the same
physical register as candidate for common subexpression elimination
in MachineCSE.

This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc
caused by MachineCSE invalidly merging two separate DYNALLOC insns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 18:40:58 +00:00

19 lines
554 B
LLVM

; RUN: llc < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define void @test(i64 %n) nounwind {
entry:
%0 = alloca i8, i64 %n, align 1
%1 = alloca i8, i64 %n, align 1
call void @use(i8* %0, i8* %1) nounwind
ret void
}
declare void @use(i8*, i8*)
; Check we actually have two instances of dynamic stack allocation,
; identified by the stdux used to update the back-chain link.
; CHECK: stdux
; CHECK: stdux