Tom Stellard 3406d882c0 R600/SI: Add more special cases for opcodes to ensureSRegLimit() ... Also factor out the register class lookup to its own function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187830 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-06 23:08:18 +00:00
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AArch64	AArch64: add initial NEON support	2013-08-01 09:20:35 +00:00
ARM	Debug Info Finder|Verifier: handle DbgLoc attached to instructions.	2013-08-06 19:38:43 +00:00
CPP	test commit: remove blank line.	2013-03-14 05:43:59 +00:00
Generic	Debug Info: clean up usage of Verify.	2013-06-28 05:43:10 +00:00
Hexagon	Refactor isInTailCallPosition handling	2013-08-06 09:12:35 +00:00
Inputs	Debug Info Verifier: verify SPs in llvm.dbg.sp.	2013-07-27 01:26:08 +00:00
Mips	Add the saving of S2. This is needed for some of the floating point	2013-08-04 23:56:53 +00:00
MSP430	Use conventional syntax for branches.	2013-07-14 18:19:44 +00:00
NVPTX	[NVPTX] Add missing patterns for i1 [s,u]int_to_fp	2013-08-06 14:13:34 +00:00
PowerPC	Add PPC64 mulli pattern	2013-08-06 17:03:03 +00:00
R600	R600/SI: Add more special cases for opcodes to ensureSRegLimit()	2013-08-06 23:08:18 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC	Allocate local registers in order for optimal coloring.	2013-07-25 18:35:14 +00:00
SystemZ	[SystemZ] Use BRCT and BRCTG to eliminate add-&-compare sequences	2013-08-05 11:23:46 +00:00
Thumb	Debug Info: update testing cases to pass verifier.	2013-07-29 18:12:58 +00:00
Thumb2	Refactor AnalyzeBranch on ARM. The previous version did not always analyze	2013-07-19 23:52:47 +00:00
X86	Debug Info Finder|Verifier: handle DbgLoc attached to instructions.	2013-08-06 19:38:43 +00:00
XCore	XCore target: Fix Vararg handling	2013-08-01 08:29:44 +00:00