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e9a23c4c57
This is the conservatively correct way because it's easy to move or replace a scalar immediate. This was incorrect in the case when the register class wasn't known from the static instruction definition, but still needed to be an SGPR. The main example of this is inlineasm has an SGPR constraint. Also start verifying the register classes of inlineasm operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285762 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.8 KiB
LLVM
69 lines
2.8 KiB
LLVM
; RUN: llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
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; GCN-LABEL: {{^}}inline_reg_constraints:
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; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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; GCN: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
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; GCN: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
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; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}]
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; GCN: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
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; GCN: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
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; GCN: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
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define void @inline_reg_constraints(i32 addrspace(1)* %ptr) {
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entry:
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%v32 = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,v"(i32 addrspace(1)* %ptr)
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%v64 = tail call <2 x i32> asm sideeffect "flat_load_dwordx2 $0, $1", "=v,v"(i32 addrspace(1)* %ptr)
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%v128 = tail call <4 x i32> asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(i32 addrspace(1)* %ptr)
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%s32 = tail call i32 asm sideeffect "s_load_dword $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
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%s64 = tail call <2 x i32> asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
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%s128 = tail call <4 x i32> asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
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%s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
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ret void
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}
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; GCN-LABEL: {{^}}inline_sreg_constraint_m0:
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; GCN: s_mov_b32 m0, -1
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; GCN-NOT: s_mov_b32 s{{[0-9]+}}, m0
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; GCN: ; use m0
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define void @inline_sreg_constraint_m0() {
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%m0 = tail call i32 asm sideeffect "s_mov_b32 m0, -1", "={M0}"()
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tail call void asm sideeffect "; use $0", "s"(i32 %m0)
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ret void
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}
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; GCN-LABEL: {{^}}inline_sreg_constraint_imm_i32:
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; GCN: s_mov_b32 [[REG:s[0-9]+]], 32
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; GCN: ; use [[REG]]
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define void @inline_sreg_constraint_imm_i32() {
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tail call void asm sideeffect "; use $0", "s"(i32 32)
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ret void
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}
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; GCN-LABEL: {{^}}inline_sreg_constraint_imm_f32:
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; GCN: s_mov_b32 [[REG:s[0-9]+]], 1.0
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; GCN: ; use [[REG]]
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define void @inline_sreg_constraint_imm_f32() {
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tail call void asm sideeffect "; use $0", "s"(float 1.0)
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ret void
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}
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; FIXME: Should be able to use s_mov_b64
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; GCN-LABEL: {{^}}inline_sreg_constraint_imm_i64:
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; GCN-DAG: s_mov_b32 s[[REG_LO:[0-9]+]], -4{{$}}
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; GCN-DAG: s_mov_b32 s[[REG_HI:[0-9]+]], -1{{$}}
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; GCN: ; use s{{\[}}[[REG_LO]]:[[REG_HI]]{{\]}}
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define void @inline_sreg_constraint_imm_i64() {
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tail call void asm sideeffect "; use $0", "s"(i64 -4)
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ret void
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}
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; GCN-LABEL: {{^}}inline_sreg_constraint_imm_f64:
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; GCN-DAG: s_mov_b32 s[[REG_LO:[0-9]+]], 0{{$}}
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; GCN-DAG: s_mov_b32 s[[REG_HI:[0-9]+]], 0x3ff00000{{$}}
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; GCN: ; use s{{\[}}[[REG_LO]]:[[REG_HI]]{{\]}}
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define void @inline_sreg_constraint_imm_f64() {
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tail call void asm sideeffect "; use $0", "s"(double 1.0)
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ret void
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}
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