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Historically, AMD internal sp3 assembler has flat_store* addr, data format. To match existing code and to enable reuse, change LLVM definitions to match. Also update MC and CodeGen tests. Differential Revision: http://reviews.llvm.org/D16927 Patch by: Nikolay Haustov git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260694 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
1.5 KiB
LLVM
47 lines
1.5 KiB
LLVM
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-unknown < %s | FileCheck %s
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; and can be eliminated
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; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range:
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; CHECK-NOT: v0
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; CHECK: {{flat|buffer}}_store_dword {{.*}}v0
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define void @test_workitem_id_x_known_max_range(i32 addrspace(1)* nocapture %out) #0 {
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entry:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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%and = and i32 %id, 1023
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_workitem_id_x_known_trunc_1_bit_range:
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; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0x1ff, v0
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; CHECK: {{flat|buffer}}_store_dword {{.*}}[[MASKED]]
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define void @test_workitem_id_x_known_trunc_1_bit_range(i32 addrspace(1)* nocapture %out) #0 {
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entry:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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%and = and i32 %id, 511
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range_m1:
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; CHECK-NOT: v0
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; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xff, v0
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; CHECK: {{flat|buffer}}_store_dword {{.*}}[[MASKED]]
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define void @test_workitem_id_x_known_max_range_m1(i32 addrspace(1)* nocapture %out) #0 {
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entry:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !1
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%and = and i32 %id, 255
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { norecurse nounwind }
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attributes #1 = { nounwind readnone }
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!0 = !{i32 0, i32 1024}
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!1 = !{i32 0, i32 1023}
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