mirror of
https://github.com/RPCSX/llvm.git
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ceb82aef81
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302641 91177308-0d34-0410-b5e6-96231b3b80d8
610 lines
20 KiB
LLVM
610 lines
20 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; fold (shl 0, x) -> 0
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define <4 x i32> @combine_vec_shl_zero(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_shl_zero:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_zero:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> zeroinitializer, %x
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ret <4 x i32> %1
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}
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; fold (shl x, c >= size(x)) -> undef
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define <4 x i32> @combine_vec_shl_outofrange0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_shl_outofrange0:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_outofrange0:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 33, i32 33, i32 33, i32 33>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_shl_outofrange1(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_shl_outofrange1:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_outofrange1:
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; AVX: # BB#0:
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 33, i32 34, i32 35, i32 36>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_shl_outofrange2(<4 x i32> %a0) {
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; SSE-LABEL: combine_vec_shl_outofrange2:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_outofrange2:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = and <4 x i32> %a0, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
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%2 = shl <4 x i32> %1, <i32 33, i32 33, i32 33, i32 33>
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ret <4 x i32> %2
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}
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; fold (shl x, 0) -> x
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define <4 x i32> @combine_vec_shl_by_zero(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_shl_by_zero:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_by_zero:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, zeroinitializer
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ret <4 x i32> %1
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}
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; if (shl x, c) is known to be zero, return 0
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define <4 x i32> @combine_vec_shl_known_zero0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_shl_known_zero0:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_known_zero0:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = and <4 x i32> %x, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
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%2 = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16>
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_shl_known_zero1(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_shl_known_zero1:
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; SSE: # BB#0:
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_known_zero1:
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; AVX: # BB#0:
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = and <4 x i32> %x, <i32 4294901760, i32 8589803520, i32 17179607040, i32 34359214080>
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%2 = shl <4 x i32> %1, <i32 16, i32 15, i32 14, i32 13>
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ret <4 x i32> %2
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}
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; fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
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define <4 x i32> @combine_vec_shl_trunc_and(<4 x i32> %x, <4 x i64> %y) {
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; SSE-LABEL: combine_vec_shl_trunc_and:
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
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; SSE-NEXT: andps {{.*}}(%rip), %xmm1
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; SSE-NEXT: pslld $23, %xmm1
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; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE-NEXT: cvttps2dq %xmm1, %xmm1
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; SSE-NEXT: pmulld %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_trunc_and:
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; AVX: # BB#0:
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; AVX-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
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; AVX-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
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; AVX-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%1 = and <4 x i64> %y, <i64 15, i64 255, i64 4095, i64 65535>
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%2 = trunc <4 x i64> %1 to <4 x i32>
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%3 = shl <4 x i32> %x, %2
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ret <4 x i32> %3
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}
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; fold (shl (shl x, c1), c2) -> (shl x, (add c1, c2))
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define <4 x i32> @combine_vec_shl_shl0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_shl_shl0:
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; SSE: # BB#0:
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; SSE-NEXT: pslld $6, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_shl0:
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; AVX: # BB#0:
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; AVX-NEXT: vpslld $6, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
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%2 = shl <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_shl_shl1(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_shl_shl1:
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; SSE: # BB#0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_shl1:
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; AVX: # BB#0:
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 0, i32 1, i32 2, i32 3>
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%2 = shl <4 x i32> %1, <i32 4, i32 5, i32 6, i32 7>
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ret <4 x i32> %2
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}
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; fold (shl (shl x, c1), c2) -> 0
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define <4 x i32> @combine_vec_shl_shlr_zero0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_shl_shlr_zero0:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_shlr_zero0:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
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%2 = shl <4 x i32> %1, <i32 20, i32 20, i32 20, i32 20>
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_shl_shl_zero1(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_shl_shl_zero1:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_shl_zero1:
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; AVX: # BB#0:
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = shl <4 x i32> %x, <i32 17, i32 18, i32 19, i32 20>
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%2 = shl <4 x i32> %1, <i32 25, i32 26, i32 27, i32 28>
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ret <4 x i32> %2
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}
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; fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
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define <8 x i32> @combine_vec_shl_ext_shl0(<8 x i16> %x) {
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; SSE-LABEL: combine_vec_shl_ext_shl0:
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; SSE: # BB#0:
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; SSE-NEXT: pmovsxwd %xmm0, %xmm2
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; SSE-NEXT: pslld $20, %xmm2
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; SSE-NEXT: pmovsxwd %xmm0, %xmm1
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; SSE-NEXT: pslld $20, %xmm1
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_ext_shl0:
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; AVX: # BB#0:
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; AVX-NEXT: vpmovsxwd %xmm0, %ymm0
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; AVX-NEXT: vpslld $20, %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = shl <8 x i16> %x, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
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%2 = sext <8 x i16> %1 to <8 x i32>
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%3 = shl <8 x i32> %2, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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ret <8 x i32> %3
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}
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define <8 x i32> @combine_vec_shl_ext_shl1(<8 x i16> %x) {
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; SSE-LABEL: combine_vec_shl_ext_shl1:
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; SSE: # BB#0:
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; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
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; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
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; SSE-NEXT: pmovsxwd %xmm1, %xmm1
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; SSE-NEXT: pmovsxwd %xmm0, %xmm0
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_ext_shl1:
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; AVX: # BB#0:
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; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpmovsxwd %xmm0, %ymm0
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; AVX-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = shl <8 x i16> %x, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
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%2 = sext <8 x i16> %1 to <8 x i32>
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%3 = shl <8 x i32> %2, <i32 31, i32 31, i32 30, i32 30, i32 29, i32 29, i32 28, i32 28>
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ret <8 x i32> %3
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}
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; fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
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define <8 x i32> @combine_vec_shl_zext_lshr0(<8 x i16> %x) {
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; SSE-LABEL: combine_vec_shl_zext_lshr0:
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; SSE: # BB#0:
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; SSE-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_zext_lshr0:
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; AVX: # BB#0:
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; AVX-NEXT: retq
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%1 = lshr <8 x i16> %x, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
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%2 = zext <8 x i16> %1 to <8 x i32>
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%3 = shl <8 x i32> %2, <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
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ret <8 x i32> %3
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}
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define <8 x i32> @combine_vec_shl_zext_lshr1(<8 x i16> %x) {
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; SSE-LABEL: combine_vec_shl_zext_lshr1:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrlw $8, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3,4,5,6],xmm1[7]
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: psrlw $4, %xmm0
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; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4,5,6],xmm1[7]
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrlw $2, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2],xmm0[3,4],xmm1[5,6],xmm0[7]
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: psrlw $1, %xmm0
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; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
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; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
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; SSE-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; SSE-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_zext_lshr1:
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; AVX: # BB#0:
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; AVX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [1,2,3,4,5,6,7,8]
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; AVX-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
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; AVX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
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; AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
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; AVX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; AVX-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = lshr <8 x i16> %x, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
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%2 = zext <8 x i16> %1 to <8 x i32>
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%3 = shl <8 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
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ret <8 x i32> %3
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}
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; fold (shl (sr[la] exact X, C1), C2) -> (shl X, (C2-C1)) if C1 <= C2
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define <4 x i32> @combine_vec_shl_ge_ashr_extact0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_shl_ge_ashr_extact0:
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; SSE: # BB#0:
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; SSE-NEXT: pslld $2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_shl_ge_ashr_extact0:
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; AVX: # BB#0:
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; AVX-NEXT: vpslld $2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = ashr exact <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
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%2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_shl_ge_ashr_extact1(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_ge_ashr_extact1:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: movdqa %xmm0, %xmm1
|
|
; SSE-NEXT: psrad $8, %xmm1
|
|
; SSE-NEXT: movdqa %xmm0, %xmm2
|
|
; SSE-NEXT: psrad $4, %xmm2
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
|
|
; SSE-NEXT: movdqa %xmm0, %xmm1
|
|
; SSE-NEXT: psrad $5, %xmm1
|
|
; SSE-NEXT: psrad $3, %xmm0
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
|
|
; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_ge_ashr_extact1:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = ashr exact <4 x i32> %x, <i32 3, i32 4, i32 5, i32 8>
|
|
%2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 8>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
; fold (shl (sr[la] exact X, C1), C2) -> (sr[la] X, (C2-C1)) if C1 > C2
|
|
define <4 x i32> @combine_vec_shl_lt_ashr_extact0(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_lt_ashr_extact0:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: psrad $2, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_lt_ashr_extact0:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpsrad $2, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = ashr exact <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
|
|
%2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
define <4 x i32> @combine_vec_shl_lt_ashr_extact1(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_lt_ashr_extact1:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: movdqa %xmm0, %xmm1
|
|
; SSE-NEXT: psrad $8, %xmm1
|
|
; SSE-NEXT: movdqa %xmm0, %xmm2
|
|
; SSE-NEXT: psrad $6, %xmm2
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
|
|
; SSE-NEXT: movdqa %xmm0, %xmm1
|
|
; SSE-NEXT: psrad $7, %xmm1
|
|
; SSE-NEXT: psrad $5, %xmm0
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
|
|
; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_lt_ashr_extact1:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = ashr exact <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
|
|
%2 = shl <4 x i32> %1, <i32 3, i32 4, i32 5, i32 8>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
; fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) if C2 > C1
|
|
define <4 x i32> @combine_vec_shl_gt_lshr0(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_gt_lshr0:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: pslld $2, %xmm0
|
|
; SSE-NEXT: pand {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_gt_lshr0:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
|
|
; AVX-NEXT: vpslld $2, %xmm0, %xmm0
|
|
; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
|
|
%2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
define <4 x i32> @combine_vec_shl_gt_lshr1(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_gt_lshr1:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: movdqa %xmm0, %xmm1
|
|
; SSE-NEXT: psrld $8, %xmm1
|
|
; SSE-NEXT: movdqa %xmm0, %xmm2
|
|
; SSE-NEXT: psrld $4, %xmm2
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
|
|
; SSE-NEXT: movdqa %xmm0, %xmm1
|
|
; SSE-NEXT: psrld $5, %xmm1
|
|
; SSE-NEXT: psrld $3, %xmm0
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
|
|
; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_gt_lshr1:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = lshr <4 x i32> %x, <i32 3, i32 4, i32 5, i32 8>
|
|
%2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 8>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
; fold (shl (srl x, c1), c2) -> (and (srl x, (sub c1, c2), MASK) if C1 >= C2
|
|
define <4 x i32> @combine_vec_shl_le_lshr0(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_le_lshr0:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: psrld $2, %xmm0
|
|
; SSE-NEXT: pand {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_le_lshr0:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
|
|
; AVX-NEXT: vpsrld $2, %xmm0, %xmm0
|
|
; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
|
|
%2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
define <4 x i32> @combine_vec_shl_le_lshr1(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_le_lshr1:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: movdqa %xmm0, %xmm1
|
|
; SSE-NEXT: psrld $8, %xmm1
|
|
; SSE-NEXT: movdqa %xmm0, %xmm2
|
|
; SSE-NEXT: psrld $6, %xmm2
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
|
|
; SSE-NEXT: movdqa %xmm0, %xmm1
|
|
; SSE-NEXT: psrld $7, %xmm1
|
|
; SSE-NEXT: psrld $5, %xmm0
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
|
|
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
|
|
; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_le_lshr1:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = lshr <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
|
|
%2 = shl <4 x i32> %1, <i32 3, i32 4, i32 5, i32 8>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
; fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
|
|
define <4 x i32> @combine_vec_shl_ashr0(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_ashr0:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: andps {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_ashr0:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
|
|
; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
|
|
%2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
define <4 x i32> @combine_vec_shl_ashr1(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_ashr1:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: andps {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_ashr1:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = ashr <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
|
|
%2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 8>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
; fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
|
|
define <4 x i32> @combine_vec_shl_add0(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_add0:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: pslld $2, %xmm0
|
|
; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_add0:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpslld $2, %xmm0, %xmm0
|
|
; AVX-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
|
|
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = add <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
|
|
%2 = shl <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
define <4 x i32> @combine_vec_shl_add1(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_add1:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_add1:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = add <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
|
|
%2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
; FIXME: fold (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)
|
|
define <4 x i32> @combine_vec_shl_or0(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_or0:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: por {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: pslld $2, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_or0:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
|
|
; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: vpslld $2, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = or <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
|
|
%2 = shl <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
define <4 x i32> @combine_vec_shl_or1(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_or1:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: por {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_or1:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = or <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
|
|
%2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
; fold (shl (mul x, c1), c2) -> (mul x, c1 << c2)
|
|
define <4 x i32> @combine_vec_shl_mul0(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_mul0:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_mul0:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1
|
|
; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = mul <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
|
|
%2 = shl <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2>
|
|
ret <4 x i32> %2
|
|
}
|
|
|
|
define <4 x i32> @combine_vec_shl_mul1(<4 x i32> %x) {
|
|
; SSE-LABEL: combine_vec_shl_mul1:
|
|
; SSE: # BB#0:
|
|
; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: combine_vec_shl_mul1:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = mul <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
|
|
%2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>
|
|
ret <4 x i32> %2
|
|
}
|