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3a1a366906
The dream of a unified check-line auto-generator for all phases of compilation is dead. The llc script has already diverged to be better at its goal, so having 2 scripts that do almost the same thing is just causing confusion. We can rip out the llc ability in update_test_checks.py next and rename it, so it will be clear that we have one script for llc check auto-generation and another for opt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305206 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
1.7 KiB
LLVM
63 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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define i32 @negate_nuw(i32 %x) {
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; CHECK-LABEL: negate_nuw:
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; CHECK: # BB#0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%neg = sub nuw i32 0, %x
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ret i32 %neg
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}
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define <4 x i32> @negate_nuw_vec(<4 x i32> %x) {
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; CHECK-LABEL: negate_nuw_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%neg = sub nuw <4 x i32> zeroinitializer, %x
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ret <4 x i32> %neg
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}
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define i8 @negate_zero_or_minsigned_nsw(i8 %x) {
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; CHECK-LABEL: negate_zero_or_minsigned_nsw:
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; CHECK: # BB#0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%signbit = and i8 %x, 128
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%neg = sub nsw i8 0, %signbit
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ret i8 %neg
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}
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define <4 x i32> @negate_zero_or_minsigned_nsw_vec(<4 x i32> %x) {
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; CHECK-LABEL: negate_zero_or_minsigned_nsw_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%signbit = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
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%neg = sub nsw <4 x i32> zeroinitializer, %signbit
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ret <4 x i32> %neg
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}
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define i8 @negate_zero_or_minsigned(i8 %x) {
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; CHECK-LABEL: negate_zero_or_minsigned:
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; CHECK: # BB#0:
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; CHECK-NEXT: shlb $7, %dil
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%signbit = shl i8 %x, 7
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%neg = sub i8 0, %signbit
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ret i8 %neg
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}
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define <4 x i32> @negate_zero_or_minsigned_vec(<4 x i32> %x) {
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; CHECK-LABEL: negate_zero_or_minsigned_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%signbit = and <4 x i32> %x, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
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%neg = sub <4 x i32> zeroinitializer, %signbit
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ret <4 x i32> %neg
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}
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