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0261597a5e
We currently generate BUILD_VECTOR as a tree of UNPCKL shuffles of the same type:
e.g. for v4f32:
Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
: unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
The issue is because we are not placing sequential vector elements together early enough, we fail to recognise many combinable patterns - consecutive scalar loads, extractions etc.
Instead, this patch unpacks progressively larger sequential vector elements together:
e.g. for v4f32:
Step 1: unpcklps 0, 2 ==> X: <?, ?, 1, 0>
: unpcklps 1, 3 ==> Y: <?, ?, 3, 2>
Step 2: unpcklpd X, Y ==> <3, 2, 1, 0>
This does mean that we are creating UNPCKL shuffle of different value types, but the relevant combines that benefit from this are quite capable of handling the additional BITCASTs that are now included in the shuffle tree.
Differential Revision: https://reviews.llvm.org/D33864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304688 91177308-0d34-0410-b5e6-96231b3b80d8
147 lines
4.5 KiB
LLVM
147 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
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; test vector shifts converted to proper SSE2 vector shifts when the shift
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; amounts are the same.
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define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
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; X32-LABEL: shift1a:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: psllq $32, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift1a:
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; X64: # BB#0: # %entry
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; X64-NEXT: psllq $32, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%shl = shl <2 x i64> %val, < i64 32, i64 32 >
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store <2 x i64> %shl, <2 x i64>* %dst
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ret void
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}
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define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
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; X32-LABEL: shift1b:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
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; X32-NEXT: psllq %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift1b:
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; X64: # BB#0: # %entry
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; X64-NEXT: movq %rsi, %xmm1
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; X64-NEXT: psllq %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%0 = insertelement <2 x i64> undef, i64 %amt, i32 0
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%1 = insertelement <2 x i64> %0, i64 %amt, i32 1
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%shl = shl <2 x i64> %val, %1
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store <2 x i64> %shl, <2 x i64>* %dst
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ret void
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}
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define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
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; X32-LABEL: shift2a:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pslld $5, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift2a:
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; X64: # BB#0: # %entry
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; X64-NEXT: pslld $5, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%shl = shl <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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; X32-LABEL: shift2b:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-NEXT: pslld %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift2b:
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; X64: # BB#0: # %entry
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; X64-NEXT: movd %esi, %xmm1
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; X64-NEXT: pslld %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%1 = insertelement <4 x i32> %0, i32 %amt, i32 1
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%2 = insertelement <4 x i32> %1, i32 %amt, i32 2
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%3 = insertelement <4 x i32> %2, i32 %amt, i32 3
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%shl = shl <4 x i32> %val, %3
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
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; X32-LABEL: shift3a:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: psllw $5, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift3a:
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; X64: # BB#0: # %entry
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; X64-NEXT: psllw $5, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%shl = shl <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
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store <8 x i16> %shl, <8 x i16>* %dst
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ret void
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}
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; Make sure the shift amount is properly zero extended.
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define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
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; X32-LABEL: shift3b:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movd %ecx, %xmm1
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; X32-NEXT: psllw %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift3b:
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; X64: # BB#0: # %entry
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; X64-NEXT: movzwl %si, %eax
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; X64-NEXT: movd %eax, %xmm1
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; X64-NEXT: psllw %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
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%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
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%2 = insertelement <8 x i16> %1, i16 %amt, i32 2
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%3 = insertelement <8 x i16> %2, i16 %amt, i32 3
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%4 = insertelement <8 x i16> %3, i16 %amt, i32 4
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%5 = insertelement <8 x i16> %4, i16 %amt, i32 5
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%6 = insertelement <8 x i16> %5, i16 %amt, i32 6
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%7 = insertelement <8 x i16> %6, i16 %amt, i32 7
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%shl = shl <8 x i16> %val, %7
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store <8 x i16> %shl, <8 x i16>* %dst
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ret void
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}
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