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8efaea8c45
Summary: This had been broken for a very long time, but nobody noticed until D14357 enabled shrink-wrapping by default. Reviewers: jroelofs, qcolombet Subscribers: tyomitch, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14986 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254444 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
1.9 KiB
LLVM
61 lines
1.9 KiB
LLVM
; RUN: llc %s -enable-shrink-wrap=true -o - | FileCheck %s
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target triple = "thumbv6m-none-none-eabi"
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@retval = global i32 0, align 4
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define i32 @test(i32 %i, i32 %argc, i8** nocapture readonly %argv) {
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%1 = icmp sgt i32 %argc, %i
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br i1 %1, label %2, label %19
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%3 = getelementptr inbounds i8*, i8** %argv, i32 %i
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%4 = load i8*, i8** %3, align 4
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%5 = load i8, i8* %4, align 1
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%6 = icmp eq i8 %5, 45
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%7 = getelementptr inbounds i8, i8* %4, i32 1
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%. = select i1 %6, i8* %7, i8* %4
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%.1 = select i1 %6, i32 -1, i32 1
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%8 = load i8, i8* %., align 1
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%.off2 = add i8 %8, -48
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%9 = icmp ult i8 %.off2, 10
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%.pre = load i32, i32* @retval, align 4
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br i1 %9, label %.lr.ph.preheader, label %.critedge
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.lr.ph.preheader: ; preds = %2
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br label %.lr.ph
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.lr.ph: ; preds = %.lr.ph.preheader, %.lr.ph
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%10 = phi i32 [ %14, %.lr.ph ], [ %.pre, %.lr.ph.preheader ]
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%11 = phi i8 [ %15, %.lr.ph ], [ %8, %.lr.ph.preheader ]
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%valstring.03 = phi i8* [ %13, %.lr.ph ], [ %., %.lr.ph.preheader ]
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%12 = zext i8 %11 to i32
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%13 = getelementptr inbounds i8, i8* %valstring.03, i32 1
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%14 = add nsw i32 %10, %12
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store i32 %14, i32* @retval, align 4
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%15 = load i8, i8* %13, align 1
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%.off = add i8 %15, -48
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%16 = icmp ult i8 %.off, 10
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br i1 %16, label %.lr.ph, label %.critedge.loopexit
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.critedge.loopexit: ; preds = %.lr.ph
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%.lcssa = phi i32 [ %14, %.lr.ph ]
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br label %.critedge
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.critedge: ; preds = %.critedge.loopexit, %2
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%17 = phi i32 [ %.pre, %2 ], [ %.lcssa, %.critedge.loopexit ]
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%18 = mul nsw i32 %17, %.1
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store i32 %18, i32* @retval, align 4
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br label %19
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; <label>:19 ; preds = %.critedge, %0
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ret i32 0
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}
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; CHECK: push {r4, r5, r7, lr}
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; CHECK: pop {r4, r5, r7}
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; CHECK: pop {r0}
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; CHECK: mov lr, r0
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; CHECK: movs r0, #0
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; CHECK: bx lr
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