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c931f35508
It turns out we decide whether to use SjLj exceptions or some alternative in two separate places in the backend, and they disagreed with each other. This led to inconsistent code and is generally a terrible idea. So make them consistent and add an assert that they *do* match (unfortunately MCAsmInfo isn't available in opt, so it can't be used to initialise the CodeGen version directly). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253502 91177308-0d34-0410-b5e6-96231b3b80d8
518 lines
14 KiB
LLVM
518 lines
14 KiB
LLVM
; RUN: llc %s -o - -enable-shrink-wrap=true -ifcvt-fn-start=1 -ifcvt-fn-stop=0 -mtriple=thumb-macho \
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; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
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; RUN: llc %s -o - -enable-shrink-wrap=false -ifcvt-fn-start=1 -ifcvt-fn-stop=0 -mtriple=thumb-macho \
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; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
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;
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; Note: Lots of tests use inline asm instead of regular calls.
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; This allows to have a better control on what the allocation will do.
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; Otherwise, we may have spill right in the entry block, defeating
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; shrink-wrapping. Moreover, some of the inline asm statements (nop)
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; are here to ensure that the related paths do not end up as critical
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; edges.
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; Also disable the late if-converter as it makes harder to reason on
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; the diffs.
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; Initial motivating example: Simple diamond with a call just on one side.
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; CHECK-LABEL: foo:
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;
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; Compare the arguments and jump to exit.
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; No prologue needed.
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; ENABLE: cmp r0, r1
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; ENABLE-NEXT: bge [[EXIT_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; CHECK: push {r7, lr}
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; CHECK: sub sp, #8
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;
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; Compare the arguments and jump to exit.
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; After the prologue is set.
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; DISABLE: cmp r0, r1
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; DISABLE-NEXT: bge [[EXIT_LABEL:LBB[0-9_]+]]
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;
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; Store %a in the alloca.
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; CHECK: str r0, [sp, #4]
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; Set the alloca address in the second argument.
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; Set the first argument to zero.
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; CHECK: movs r0, #0
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; CHECK-NEXT: add r1, sp, #4
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; CHECK-NEXT: bl
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;
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; With shrink-wrapping, epilogue is just after the call.
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; ENABLE-NEXT: add sp, #8
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; ENABLE-NEXT: pop {r7, lr}
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;
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; CHECK: [[EXIT_LABEL]]:
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;
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; Without shrink-wrapping, epilogue is in the exit block.
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; Epilogue code. (What we pop does not matter.)
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; DISABLE: add sp, #8
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; DISABLE-NEXT: pop {r7, pc}
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;
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; ENABLE-NEXT: bx lr
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define i32 @foo(i32 %a, i32 %b) {
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%tmp = alloca i32, align 4
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%tmp2 = icmp slt i32 %a, %b
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br i1 %tmp2, label %true, label %false
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true:
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store i32 %a, i32* %tmp, align 4
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%tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
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br label %false
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false:
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%tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
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ret i32 %tmp.0
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}
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; Function Attrs: optsize
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declare i32 @doSomething(i32, i32*)
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; Check that we do not perform the restore inside the loop whereas the save
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; is outside.
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; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
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;
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; Shrink-wrapping allows to skip the prologue in the else case.
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; ENABLE: cmp r0, #0
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; ENABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: r4.
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; CHECK: push {r4, lr}
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;
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; DISABLE: cmp r0, #0
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; DISABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; SUM is in r0 because it is coalesced with the second
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; argument on the else path.
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; CHECK: movs [[SUM:r0]], #0
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; CHECK-NEXT: movs [[IV:r[0-9]+]], #10
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;
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; Next BB.
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; CHECK: [[LOOP:LBB[0-9_]+]]: @ %for.body
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; CHECK: movs [[TMP:r[0-9]+]], #1
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; CHECK: adds [[SUM]], [[TMP]], [[SUM]]
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; CHECK-NEXT: subs [[IV]], [[IV]], #1
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; CHECK-NEXT: cmp [[IV]], #0
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; CHECK-NEXT: bne [[LOOP]]
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;
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; Next BB.
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; SUM << 3.
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; CHECK: lsls [[SUM]], [[SUM]], #3
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;
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; Duplicated epilogue.
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; DISABLE: pop {r4, pc}
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;
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; CHECK: [[ELSE_LABEL]]: @ %if.else
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; Shift second argument by one and store into returned register.
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; CHECK: lsls r0, r1, #1
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; DISABLE-NEXT: pop {r4, pc}
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;
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; ENABLE-NEXT: bx lr
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define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {
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entry:
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%tobool = icmp eq i32 %cond, 0
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br i1 %tobool, label %if.else, label %for.preheader
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for.preheader:
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tail call void asm "nop", ""()
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
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%sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
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%call = tail call i32 asm sideeffect "movs $0, #1", "=r,~{r4}"()
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%add = add nsw i32 %call, %sum.04
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%inc = add nuw nsw i32 %i.05, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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%shl = shl i32 %add, 3
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br label %if.end
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if.else: ; preds = %entry
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%mul = shl nsw i32 %N, 1
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br label %if.end
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if.end: ; preds = %if.else, %for.end
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%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
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ret i32 %sum.1
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}
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declare i32 @something(...)
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; Check that we do not perform the shrink-wrapping inside the loop even
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; though that would be legal. The cost model must prevent that.
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; CHECK-LABEL: freqSaveAndRestoreOutsideLoop2:
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: r4.
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; CHECK: push {r4
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; This is the nop.
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; CHECK: mov r8, r8
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; CHECK: movs [[SUM:r0]], #0
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; CHECK-NEXT: movs [[IV:r[0-9]+]], #10
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; Next BB.
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; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: @ %for.body
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; CHECK: movs [[TMP:r[0-9]+]], #1
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; CHECK: adds [[SUM]], [[TMP]], [[SUM]]
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; CHECK-NEXT: subs [[IV]], [[IV]], #1
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; CHECK-NEXT: cmp [[IV]], #0
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; CHECK-NEXT: bne [[LOOP_LABEL]]
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; Next BB.
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; CHECK: @ %for.exit
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; This is the nop.
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; CHECK: mov r8, r8
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; CHECK: pop {r4
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define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
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entry:
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br label %for.preheader
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for.preheader:
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tail call void asm "nop", ""()
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.04 = phi i32 [ 0, %for.preheader ], [ %inc, %for.body ]
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%sum.03 = phi i32 [ 0, %for.preheader ], [ %add, %for.body ]
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%call = tail call i32 asm sideeffect "movs $0, #1", "=r,~{r4}"()
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%add = add nsw i32 %call, %sum.03
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%inc = add nuw nsw i32 %i.04, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.exit, label %for.body
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for.exit:
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tail call void asm "nop", ""()
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br label %for.end
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for.end: ; preds = %for.body
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ret i32 %add
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}
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; Check with a more complex case that we do not have save within the loop and
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; restore outside.
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; CHECK-LABEL: loopInfoSaveOutsideLoop:
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;
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; ENABLE: cmp r0, #0
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; ENABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: r4.
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; CHECK: push {r4, lr}
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;
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; DISABLE: cmp r0, #0
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; DISABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; SUM is in r0 because it is coalesced with the second
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; argument on the else path.
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; CHECK: movs [[SUM:r0]], #0
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; CHECK-NEXT: movs [[IV:r[0-9]+]], #10
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;
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; Next BB.
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; CHECK: [[LOOP:LBB[0-9_]+]]: @ %for.body
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; CHECK: movs [[TMP:r[0-9]+]], #1
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; CHECK: adds [[SUM]], [[TMP]], [[SUM]]
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; CHECK-NEXT: subs [[IV]], [[IV]], #1
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; CHECK-NEXT: cmp [[IV]], #0
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; CHECK-NEXT: bne [[LOOP]]
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;
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; Next BB.
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; SUM << 3.
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; CHECK: lsls [[SUM]], [[SUM]], #3
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; ENABLE-NEXT: pop {r4, lr}
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;
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; Duplicated epilogue.
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; DISABLE: pop {r4, pc}
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;
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; CHECK: [[ELSE_LABEL]]: @ %if.else
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; Shift second argument by one and store into returned register.
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; CHECK: lsls r0, r1, #1
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; DISABLE-NEXT: pop {r4, pc}
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;
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; ENABLE-NEXT: bx lr
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define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
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entry:
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%tobool = icmp eq i32 %cond, 0
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br i1 %tobool, label %if.else, label %for.preheader
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for.preheader:
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tail call void asm "nop", ""()
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
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%sum.04 = phi i32 [ %add, %for.body ], [ 0, %for.preheader ]
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%call = tail call i32 asm sideeffect "movs $0, #1", "=r,~{r4}"()
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%add = add nsw i32 %call, %sum.04
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%inc = add nuw nsw i32 %i.05, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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tail call void asm "nop", "~{r4}"()
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%shl = shl i32 %add, 3
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br label %if.end
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if.else: ; preds = %entry
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%mul = shl nsw i32 %N, 1
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br label %if.end
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if.end: ; preds = %if.else, %for.end
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%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
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ret i32 %sum.1
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}
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declare void @somethingElse(...)
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; Check with a more complex case that we do not have restore within the loop and
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; save outside.
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; CHECK-LABEL: loopInfoRestoreOutsideLoop:
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;
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; ENABLE: cmp r0, #0
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; ENABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: r4.
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; CHECK: push {r4, lr}
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;
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; DISABLE-NEXT: cmp r0, #0
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; DISABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; SUM is in r0 because it is coalesced with the second
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; argument on the else path.
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; CHECK: movs [[SUM:r0]], #0
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; CHECK-NEXT: movs [[IV:r[0-9]+]], #10
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;
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; Next BB.
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; CHECK: [[LOOP:LBB[0-9_]+]]: @ %for.body
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; CHECK: movs [[TMP:r[0-9]+]], #1
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; CHECK: adds [[SUM]], [[TMP]], [[SUM]]
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; CHECK-NEXT: subs [[IV]], [[IV]], #1
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; CHECK-NEXT: cmp [[IV]], #0
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; CHECK-NEXT: bne [[LOOP]]
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;
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; Next BB.
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; SUM << 3.
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; CHECK: lsls [[SUM]], [[SUM]], #3
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; ENABLE: pop {r4, lr}
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;
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; Duplicated epilogue.
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; DISABLE: pop {r4, pc}
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;
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; CHECK: [[ELSE_LABEL]]: @ %if.else
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; Shift second argument by one and store into returned register.
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; CHECK: lsls r0, r1, #1
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; DISABLE-NEXT: pop {r4, pc}
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;
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; ENABLE-NEXT: bx lr
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define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) #0 {
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entry:
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%tobool = icmp eq i32 %cond, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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tail call void asm "nop", "~{r4}"()
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br label %for.body
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for.body: ; preds = %for.body, %if.then
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%i.05 = phi i32 [ 0, %if.then ], [ %inc, %for.body ]
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%sum.04 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
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%call = tail call i32 asm sideeffect "movs $0, #1", "=r,~{r4}"()
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%add = add nsw i32 %call, %sum.04
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%inc = add nuw nsw i32 %i.05, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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%shl = shl i32 %add, 3
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br label %if.end
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if.else: ; preds = %entry
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%mul = shl nsw i32 %N, 1
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br label %if.end
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if.end: ; preds = %if.else, %for.end
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%sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
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ret i32 %sum.1
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}
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; Check that we handle function with no frame information correctly.
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; CHECK-LABEL: emptyFrame:
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; CHECK: @ %entry
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: bx lr
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define i32 @emptyFrame() {
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entry:
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ret i32 0
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}
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; Check that we handle inline asm correctly.
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; CHECK-LABEL: inlineAsm:
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;
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; ENABLE: cmp r0, #0
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; ENABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; Make sure we save the CSR used in the inline asm: r4.
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; CHECK: push {r4, lr}
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;
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; DISABLE: cmp r0, #0
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; DISABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; CHECK: movs [[IV:r[0-9]+]], #10
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;
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; Next BB.
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; CHECK: [[LOOP:LBB[0-9_]+]]: @ %for.body
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; CHECK: movs r4, #1
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; CHECK: subs [[IV]], [[IV]], #1
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; CHECK-NEXT: cmp [[IV]], #0
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; CHECK-NEXT: bne [[LOOP]]
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;
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; Next BB.
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; CHECK: movs r0, #0
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; ENABLE-NEXT: pop {r4, lr}
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;
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; Duplicated epilogue.
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; DISABLE-NEXT: pop {r4, pc}
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;
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; CHECK: [[ELSE_LABEL]]: @ %if.else
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; Shift second argument by one and store into returned register.
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; CHECK: lsls r0, r1, #1
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; DISABLE-NEXT: pop {r4, pc}
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;
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; ENABLE-NEXT: bx lr
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define i32 @inlineAsm(i32 %cond, i32 %N) {
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entry:
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%tobool = icmp eq i32 %cond, 0
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br i1 %tobool, label %if.else, label %for.preheader
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for.preheader:
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tail call void asm "nop", ""()
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.03 = phi i32 [ %inc, %for.body ], [ 0, %for.preheader ]
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tail call void asm sideeffect "movs r4, #1", "~{r4}"()
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%inc = add nuw nsw i32 %i.03, 1
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%exitcond = icmp eq i32 %inc, 10
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br i1 %exitcond, label %for.exit, label %for.body
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for.exit:
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tail call void asm "nop", ""()
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br label %if.end
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if.else: ; preds = %entry
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%mul = shl nsw i32 %N, 1
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br label %if.end
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if.end: ; preds = %for.body, %if.else
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%sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ]
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ret i32 %sum.0
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}
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; Check that we handle calls to variadic functions correctly.
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; CHECK-LABEL: callVariadicFunc:
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;
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; ENABLE: cmp r0, #0
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; ENABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Prologue code.
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; CHECK: push {[[TMP:r[0-9]+]], lr}
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; CHECK: sub sp, #16
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;
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; DISABLE: cmp r0, #0
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; DISABLE-NEXT: beq [[ELSE_LABEL:LBB[0-9_]+]]
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;
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; Setup of the varags.
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; CHECK: mov [[TMP_SP:r[0-9]+]], sp
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; CHECK-NEXT: str r1, {{\[}}[[TMP_SP]]]
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; CHECK-NEXT: str r1, {{\[}}[[TMP_SP]], #4]
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; CHECK-NEXT: str r1, {{\[}}[[TMP_SP]], #8]
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; Thumb has quite a strange way for moving stuff
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; in around. Oh well, match the current sequence.
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; CHECK: push {r1}
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; CHECK-NEXT: pop {r0}
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; CHECK: push {r1}
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; CHECK-NEXT: pop {r2}
|
|
; CHECK: push {r1}
|
|
; CHECK-NEXT: pop {r3}
|
|
; CHECK-NEXT: bl
|
|
; CHECK-NEXT: lsls r0, r0, #3
|
|
; CHECK-NEXT: add sp, #16
|
|
;
|
|
; ENABLE-NEXT: pop {[[TMP]], lr}
|
|
;
|
|
; Duplicated epilogue.
|
|
; DISABLE-NEXT: pop {[[TMP]], pc}
|
|
;
|
|
; CHECK: [[ELSE_LABEL]]: @ %if.else
|
|
; Shift second argument by one and store into returned register.
|
|
; CHECK: lsls r0, r1, #1
|
|
;
|
|
; Epilogue code.
|
|
; ENABLE-NEXT: bx lr
|
|
;
|
|
; DISABLE-NEXT: add sp, #16
|
|
; DISABLE-NEXT: pop {[[TMP]], pc}
|
|
define i32 @callVariadicFunc(i32 %cond, i32 %N) {
|
|
entry:
|
|
%tobool = icmp eq i32 %cond, 0
|
|
br i1 %tobool, label %if.else, label %if.then
|
|
|
|
if.then: ; preds = %entry
|
|
%call = tail call i32 (i32, ...) @someVariadicFunc(i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N, i32 %N)
|
|
%shl = shl i32 %call, 3
|
|
br label %if.end
|
|
|
|
if.else: ; preds = %entry
|
|
%mul = shl nsw i32 %N, 1
|
|
br label %if.end
|
|
|
|
if.end: ; preds = %if.else, %if.then
|
|
%sum.0 = phi i32 [ %shl, %if.then ], [ %mul, %if.else ]
|
|
ret i32 %sum.0
|
|
}
|
|
|
|
declare i32 @someVariadicFunc(i32, ...)
|
|
|
|
; Make sure we do not insert unreachable code after noreturn function.
|
|
; Although this is not incorrect to insert such code, it is useless
|
|
; and it hurts the binary size.
|
|
;
|
|
; CHECK-LABEL: noreturn:
|
|
; DISABLE: push
|
|
;
|
|
; CHECK: movs [[TMP:r[0-9]+]], #255
|
|
; CHECK-NEXT: tst r0, [[TMP]]
|
|
; CHECK-NEXT: bne [[ABORT:LBB[0-9_]+]]
|
|
;
|
|
; CHECK: movs r0, #42
|
|
;
|
|
; ENABLE-NEXT: bx lr
|
|
;
|
|
; DISABLE-NEXT: pop
|
|
;;
|
|
; CHECK: [[ABORT]]: @ %if.abort
|
|
;
|
|
; ENABLE: push
|
|
;
|
|
; CHECK: bl
|
|
; ENABLE-NOT: pop
|
|
define i32 @noreturn(i8 signext %bad_thing) {
|
|
entry:
|
|
%tobool = icmp eq i8 %bad_thing, 0
|
|
br i1 %tobool, label %if.end, label %if.abort
|
|
|
|
if.abort:
|
|
%call = tail call i32 asm sideeffect "movs $0, #1", "=r,~{r4}"()
|
|
tail call void @abort() #0
|
|
unreachable
|
|
|
|
if.end:
|
|
ret i32 42
|
|
}
|
|
|
|
declare void @abort() #0
|
|
|
|
attributes #0 = { noreturn nounwind }
|