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d9fcabcdd3
This script prints a CSV of all misched models of a target when given the output of the debug output of subtarget using:
llvm-tblgen --gen-subtarget --debug-only=subtarget-emitter ...
With thanks to Dave Estes for mentioning the idea at the 2014 LLVM Developers' Meeting.
Patch by Christof Douma!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250020 91177308-0d34-0410-b5e6-96231b3b80d8
78 lines
2.3 KiB
Python
78 lines
2.3 KiB
Python
#!/usr/bin/python
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# This creates a CSV file from the output of the debug output of subtarget:
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# llvm-tblgen --gen-subtarget --debug-only=subtarget-emitter
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# With thanks to Dave Estes for mentioning the idea at 2014 LLVM Developers' Meeting
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import os;
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import sys;
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import re;
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import operator;
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table = {}
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models = set()
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filt = None
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def add(instr, model, resource=None):
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global table, models
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entry = table.setdefault(instr, dict())
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entry[model] = resource
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models.add(model)
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def filter_model(m):
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global filt
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if m and filt:
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return filt.search(m) != None
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else:
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return True
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def display():
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global table, models
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ordered_table = sorted(table.items(), key=operator.itemgetter(0))
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ordered_models = filter(filter_model, sorted(models))
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# print header
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sys.stdout.write("instruction")
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for model in ordered_models:
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if not model: model = "default"
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sys.stdout.write(", {}".format(model))
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sys.stdout.write(os.linesep)
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for (instr, mapping) in ordered_table:
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sys.stdout.write(instr)
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for model in ordered_models:
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if model in mapping:
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sys.stdout.write(", {}".format(mapping[model]))
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else:
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sys.stdout.write(", ")
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sys.stdout.write(os.linesep)
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def machineModelCover(path):
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# The interesting bits
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re_sched_default = re.compile("SchedRW machine model for ([^ ]*) (.*)\n");
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re_sched_no_default = re.compile("No machine model for ([^ ]*)\n");
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re_sched_spec = re.compile("InstRW on ([^ ]*) for ([^ ]*) (.*)\n");
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re_sched_no_spec = re.compile("No machine model for ([^ ]*) on processor (.*)\n");
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# scan the file
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with open(path, 'r') as f:
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for line in f.readlines():
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match = re_sched_default.match(line)
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if match: add(match.group(1), None, match.group(2))
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match = re_sched_no_default.match(line)
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if match: add(match.group(1), None)
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match = re_sched_spec.match(line)
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if match: add(match.group(2), match.group(1), match.group(3))
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match = re_sched_no_default.match(line)
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if match: add(match.group(1), None)
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display()
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if len(sys.argv) > 2:
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filt = re.compile(sys.argv[2], re.IGNORECASE)
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machineModelCover(sys.argv[1])
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