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67f335d992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283004 91177308-0d34-0410-b5e6-96231b3b80d8
148 lines
4.8 KiB
C++
148 lines
4.8 KiB
C++
//===-- MipsHazardSchedule.cpp - Workaround pipeline hazards --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This pass is used to workaround certain pipeline hazards. For now, this covers
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/// compact branch hazards. In future this pass can be extended to other pipeline
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/// hazards, such as various MIPS1 hazards, processor errata that require
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/// instruction reorganization, etc.
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///
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/// This pass has to run after the delay slot filler as that pass can introduce
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/// pipeline hazards, hence the existing hazard recognizer is not suitable.
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///
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/// Hazards handled: forbidden slots for MIPSR6.
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///
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/// A forbidden slot hazard occurs when a compact branch instruction is executed
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/// and the adjacent instruction in memory is a control transfer instruction such
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/// as a branch or jump, ERET, ERETNC, DERET, WAIT and PAUSE.
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///
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/// For example:
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///
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/// 0x8004 bnec a1,v0,<P+0x18>
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/// 0x8008 beqc a1,a2,<P+0x54>
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///
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/// In such cases, the processor is required to signal a Reserved Instruction
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/// exception.
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///
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/// Here, if the instruction at 0x8004 is executed, the processor will raise an
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/// exception as there is a control transfer instruction at 0x8008.
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///
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/// There are two sources of forbidden slot hazards:
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///
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/// A) A previous pass has created a compact branch directly.
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/// B) Transforming a delay slot branch into compact branch. This case can be
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/// difficult to process as lookahead for hazards is insufficent, as
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/// backwards delay slot fillling can also produce hazards in previously
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/// processed instuctions.
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///
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsInstrInfo.h"
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#include "MipsSEInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-hazard-schedule"
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STATISTIC(NumInsertedNops, "Number of nops inserted");
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namespace {
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typedef MachineBasicBlock::iterator Iter;
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typedef MachineBasicBlock::reverse_iterator ReverseIter;
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class MipsHazardSchedule : public MachineFunctionPass {
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public:
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MipsHazardSchedule() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return "Mips Hazard Schedule"; }
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bool runOnMachineFunction(MachineFunction &F) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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private:
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static char ID;
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};
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char MipsHazardSchedule::ID = 0;
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} // end of anonymous namespace
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/// Returns a pass that clears pipeline hazards.
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FunctionPass *llvm::createMipsHazardSchedule() {
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return new MipsHazardSchedule();
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}
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// Find the next real instruction from the current position.
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static Iter getNextMachineInstr(Iter Position) {
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Iter I = Position, E = Position->getParent()->end();
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I = std::find_if_not(I, E, [](const Iter &Insn) { return Insn->isTransient(); });
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assert(I != E);
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return I;
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}
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bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) {
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const MipsSubtarget *STI =
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&static_cast<const MipsSubtarget &>(MF.getSubtarget());
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// Forbidden slot hazards are only defined for MIPSR6.
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if (!STI->hasMips32r6() || STI->inMicroMipsMode())
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return false;
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bool Changed = false;
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const MipsInstrInfo *TII = STI->getInstrInfo();
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for (MachineFunction::iterator FI = MF.begin(); FI != MF.end(); ++FI) {
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for (Iter I = FI->begin(); I != FI->end(); ++I) {
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// Forbidden slot hazard handling. Use lookahead over state.
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if (!TII->HasForbiddenSlot(*I))
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continue;
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bool InsertNop = false;
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// Next instruction in the basic block.
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if (std::next(I) != FI->end() &&
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!TII->SafeInForbiddenSlot(*getNextMachineInstr(std::next(I)))) {
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InsertNop = true;
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} else {
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// Next instruction in the physical successor basic block.
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for (auto *Succ : FI->successors()) {
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if (FI->isLayoutSuccessor(Succ) &&
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getNextMachineInstr(Succ->begin()) != Succ->end() &&
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!TII->SafeInForbiddenSlot(*getNextMachineInstr(Succ->begin()))) {
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InsertNop = true;
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break;
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}
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}
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}
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if (InsertNop) {
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Changed = true;
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MIBundleBuilder(&*I).append(
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BuildMI(MF, I->getDebugLoc(), TII->get(Mips::NOP)));
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NumInsertedNops++;
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}
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}
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}
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return Changed;
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}
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