llvm/test/MC/X86/x86-branch-relaxation.s
Nirav Dave 6b00c9f9a9 Fix branch relaxation in 16-bit mode.
Thread through MCSubtargetInfo to relaxInstruction function allowing relaxation
to generate jumps with 16-bit sized immediates in 16-bit mode.

This fixes PR22097.

Reviewers: dwmw2, tstellarAMD, craig.topper, jyknight

Subscribers: jfb, arsenm, jyknight, llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D20830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275068 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-11 14:23:53 +00:00

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ArmAsm

# RUN: llvm-mc -filetype=obj -triple=i386-unknown-unknown %s -o %t
# RUN: llvm-objdump -r -D -section .text.bar -triple i386-unknown-unknown-code16 %t | FileCheck --check-prefix=CHECK16 %s
# RUN: llvm-objdump -r -D -section .text.baz -triple i386-unknown-unknown %t | FileCheck --check-prefix=CHECK32 %s
.text
.section .text.foo,"",@progbits
.code16
.globl foo
foo:
nop
.section .text.bar,"",@progbits
.globl bar16
bar16:
jmp foo
.section .text.baz,"",@progbits
.code32
.globl baz32
baz32:
jmp foo
// CHECK16-LABEL: bar16
// CHECK16-NEXT: e9 fe ff jmp -2 <bar16+0x1>
// CHECK32-LABEL: baz32
// CHECK32-NEXT: e9 fc ff ff ff jmp -4 <baz32+0x1>