llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt
Hal Finkel 184f8f7c10 [PowerPC] Enable printing instructions using aliases
TableGen had been nicely generating code to print a number of instructions using
shorter aliases (and PowerPC has plenty of short mnemonics), but we were not
calling it. For some of the aliases we support in the parser, TableGen can't
infer the "inverse" alias relationship, so there is still more to do.

Thus, after some hours of updating test cases...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 18:30:38 +00:00

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# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s
# CHECK: add 1, 2, 3
0x7c 0x22 0x1a 0x14
# CHECK: add 1, 2, 3
0x7c 0x22 0x1a 0x14
# CHECK: add 0, 0, 0
0x7c 0x00 0x02 0x14
# CHECK: add 31, 31, 31
0x7f 0xff 0xfa 0x14
# CHECK: li 1, 0
0x38 0x20 0x00 0x00
# CHECK: addi 1, 2, 0
0x38 0x22 0x00 0x00
# CHECK: li 1, -32768
0x38 0x20 0x80 0x00
# CHECK: li 1, 32767
0x38 0x20 0x7f 0xff
# CHECK: ori 1, 2, 0
0x60 0x41 0x00 0x00
# CHECK: ori 1, 2, 65535
0x60 0x41 0xff 0xff
# CHECK: lis 1, 0
0x3c 0x20 0x00 0x00
# CHECK: lis 1, -1
0x3c 0x20 0xff 0xff
# CHECK: lwz 1, 0(0)
0x80 0x20 0x00 0x00
# CHECK: lwz 1, 0(0)
0x80 0x20 0x00 0x00
# CHECK: lwz 1, 0(31)
0x80 0x3f 0x00 0x00
# CHECK: lwz 1, 0(31)
0x80 0x3f 0x00 0x00
# CHECK: lwz 1, -32768(2)
0x80 0x22 0x80 0x00
# CHECK: lwz 1, 32767(2)
0x80 0x22 0x7f 0xff
# CHECK: ld 1, 0(0)
0xe8 0x20 0x00 0x00
# CHECK: ld 1, 0(0)
0xe8 0x20 0x00 0x00
# CHECK: ld 1, 0(31)
0xe8 0x3f 0x00 0x00
# CHECK: ld 1, 0(31)
0xe8 0x3f 0x00 0x00
# CHECK: ld 1, -32768(2)
0xe8 0x22 0x80 0x00
# CHECK: ld 1, 32764(2)
0xe8 0x22 0x7f 0xfc
# CHECK: ld 1, 4(2)
0xe8 0x22 0x00 0x04
# CHECK: ld 1, -4(2)
0xe8 0x22 0xff 0xfc
# CHECK: b .+1024
0x48 0x00 0x04 0x00
# CHECK: ba 1024
0x48 0x00 0x04 0x02
# FIXME: decode as beq 0, .+1024
# CHECK: bt 2, .+1024
0x41 0x82 0x04 0x00
# FIXME: decode as beqa 0, 1024
# CHECK: bta 2, 1024
0x41 0x82 0x04 0x02