llvm/lib/Target/Sparc
Dale Johannesen aafce77b17 Add CommonLinkage; currently tentative definitions
are represented as "weak", but there are subtle differences
in some cases on Darwin, so we need both.  The intent
is that "common" will behave identically to "weak" unless
somebody changes their target to do something else.
No functional change as yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51118 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-14 20:12:51 +00:00
..
DelaySlotFiller.cpp rename TargetInstrDescriptor -> TargetInstrDesc. 2008-01-07 07:27:27 +00:00
FPMover.cpp rename MachineInstr::setInstrDescriptor -> setDesc 2008-01-11 18:10:50 +00:00
Makefile Start moving sparc to use SparcCallingConv.td, switching over 2008-03-17 05:41:48 +00:00
README.txt fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105 2008-02-28 05:44:20 +00:00
Sparc.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
Sparc.td Start moving sparc to use SparcCallingConv.td, switching over 2008-03-17 05:41:48 +00:00
SparcAsmPrinter.cpp Add CommonLinkage; currently tentative definitions 2008-05-14 20:12:51 +00:00
SparcCallingConv.td Check in some #ifdef'd out code switching call argument 2008-03-17 06:58:37 +00:00
SparcInstrFormats.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcInstrInfo.cpp It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. 2008-02-08 21:20:40 +00:00
SparcInstrInfo.h Change target-specific classes to use more precise static types. 2008-05-14 01:58:56 +00:00
SparcInstrInfo.td Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 2008-03-15 00:03:38 +00:00
SparcISelDAGToDAG.cpp split sparc lowering out into SparcISelLowering.{cpp|h} to follow 2008-03-17 03:21:36 +00:00
SparcISelLowering.cpp Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal 2008-04-12 04:36:06 +00:00
SparcISelLowering.h Switch sparc from using LowerCallTo to using LowerOperation(CALL) like 2008-03-17 06:01:07 +00:00
SparcRegisterInfo.cpp Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. 2008-03-31 20:40:39 +00:00
SparcRegisterInfo.h Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. 2008-03-31 20:40:39 +00:00
SparcRegisterInfo.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcSubtarget.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcSubtarget.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcTargetAsmInfo.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcTargetAsmInfo.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcTargetMachine.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
SparcTargetMachine.h Change target-specific classes to use more precise static types. 2008-05-14 01:58:56 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots